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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 15:38:48 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 15:38:48 -0800 |
| commit | bd56161775f47a474aaf5153d2273b86dad4f6f4 (patch) | |
| tree | f4f8bc875eb0cebec0919e997a73b6b3afc36564 /frontends/verific/verific.h | |
| parent | 8ef241c6f4a976dca67760c43e820d4e812f2fc2 (diff) | |
| parent | 450ad0e9ba031fbeef904746ca773e3b0e21af8f (diff) | |
| download | yosys-bd56161775f47a474aaf5153d2273b86dad4f6f4.tar.gz yosys-bd56161775f47a474aaf5153d2273b86dad4f6f4.tar.bz2 yosys-bd56161775f47a474aaf5153d2273b86dad4f6f4.zip | |
Merge branch 'eddie/clkpart' into xaig_dff
Diffstat (limited to 'frontends/verific/verific.h')
| -rw-r--r-- | frontends/verific/verific.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index 5cbd78f7b..2ccfcd42c 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -93,7 +93,7 @@ struct VerificImporter void merge_past_ffs_clock(pool<RTLIL::Cell*> &candidates, SigBit clock, bool clock_pol); void merge_past_ffs(pool<RTLIL::Cell*> &candidates); - void import_netlist(RTLIL::Design *design, Verific::Netlist *nl, std::set<Verific::Netlist*> &nl_todo); + void import_netlist(RTLIL::Design *design, Verific::Netlist *nl, std::set<Verific::Netlist*> &nl_todo, bool norename = false); }; void verific_import_sva_assert(VerificImporter *importer, Verific::Instance *inst); |