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| author | Clifford Wolf <clifford@clifford.at> | 2018-06-01 13:25:42 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-06-01 13:25:42 +0200 |
| commit | 4372cf690d829755279a6a5778023e5e0a4493b2 (patch) | |
| tree | 1598748761fe015b7f95b4c3c89679f36ccd7f0a /frontends/verific/verific.h | |
| parent | f273291dfe5de460192ef2a63a121b3c2e8b9a62 (diff) | |
| download | yosys-4372cf690d829755279a6a5778023e5e0a4493b2.tar.gz yosys-4372cf690d829755279a6a5778023e5e0a4493b2.tar.bz2 yosys-4372cf690d829755279a6a5778023e5e0a4493b2.zip | |
Add (* gclk *) attribute support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verific/verific.h')
| -rw-r--r-- | frontends/verific/verific.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index 714b7c82a..86a743ea1 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -40,6 +40,7 @@ struct VerificClocking { SigBit enable_sig = State::S1; SigBit disable_sig = State::S0; bool posedge = true; + bool gclk = false; VerificClocking() { } VerificClocking(VerificImporter *importer, Verific::Net *net, bool sva_at_only = false); |