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author | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 15:13:18 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 15:13:18 -0800 |
commit | 2a54fa41c40969841ba0574ba725caa436b0212f (patch) | |
tree | 1dbf518fc73dbe253612bdb5e466c50b78bce44b /frontends/verific/verific.h | |
parent | 6b9f90de789b1d0daf93ac1d2b608b057e7ca272 (diff) | |
parent | c03b6a3e9cab9fc05b2d5b256676f5ddc6c2d763 (diff) | |
download | yosys-2a54fa41c40969841ba0574ba725caa436b0212f.tar.gz yosys-2a54fa41c40969841ba0574ba725caa436b0212f.tar.bz2 yosys-2a54fa41c40969841ba0574ba725caa436b0212f.zip |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'frontends/verific/verific.h')
-rw-r--r-- | frontends/verific/verific.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h index 5cbd78f7b..2ccfcd42c 100644 --- a/frontends/verific/verific.h +++ b/frontends/verific/verific.h @@ -93,7 +93,7 @@ struct VerificImporter void merge_past_ffs_clock(pool<RTLIL::Cell*> &candidates, SigBit clock, bool clock_pol); void merge_past_ffs(pool<RTLIL::Cell*> &candidates); - void import_netlist(RTLIL::Design *design, Verific::Netlist *nl, std::set<Verific::Netlist*> &nl_todo); + void import_netlist(RTLIL::Design *design, Verific::Netlist *nl, std::set<Verific::Netlist*> &nl_todo, bool norename = false); }; void verific_import_sva_assert(VerificImporter *importer, Verific::Instance *inst); |