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| author | Clifford Wolf <clifford@clifford.at> | 2018-07-16 15:32:26 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-07-16 15:32:26 +0200 |
| commit | f39b897545c0f9b4d02c77cc7b6cd2a3bfc6082f (patch) | |
| tree | fa2685ebbe232957759d93f055e23b6ce0fd47ac /frontends/verific/verific.cc | |
| parent | 8b92ddb9d2635c30636b17ff3d24bc09a44b8551 (diff) | |
| download | yosys-f39b897545c0f9b4d02c77cc7b6cd2a3bfc6082f.tar.gz yosys-f39b897545c0f9b4d02c77cc7b6cd2a3bfc6082f.tar.bz2 yosys-f39b897545c0f9b4d02c77cc7b6cd2a3bfc6082f.zip | |
Add "read -incdir"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verific/verific.cc')
| -rw-r--r-- | frontends/verific/verific.cc | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 62a8028b8..ab752b96d 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -2186,6 +2186,11 @@ struct ReadPass : public Pass { log("\n"); log("Unset global Verilog/SystemVerilog defines.\n"); log("\n"); + log("\n"); + log(" read -incdir <directory>\n"); + log("\n"); + log("Add directory to global Verilog/SystemVerilog include directories.\n"); + log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { @@ -2263,6 +2268,20 @@ struct ReadPass : public Pass { return; } + if (args[1] == "-incdir") { + if (use_verific) { + args[0] = "verific"; + args[1] = "-vlog-incdir"; + Pass::call(design, args); + } + args[0] = "verilog_defaults"; + args[1] = "-add"; + for (int i = 1; i < GetSize(args); i++) + args[i] = "-I" + args[i]; + Pass::call(design, args); + return; + } + log_cmd_error("Missing or unsupported mode parameter.\n"); } } ReadPass; |