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| author | Clifford Wolf <clifford@clifford.at> | 2014-03-20 13:40:01 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-03-20 13:40:01 +0100 |
| commit | a3b9692a68e88bbe3e32e0dbbd30c5e20f3800b7 (patch) | |
| tree | 6bb72c13abdb6642c226657929246c9bba428610 /frontends/verific/verific.cc | |
| parent | 470c2455e471318f4528da597e0dd8c7499b47ce (diff) | |
| download | yosys-a3b9692a68e88bbe3e32e0dbbd30c5e20f3800b7.tar.gz yosys-a3b9692a68e88bbe3e32e0dbbd30c5e20f3800b7.tar.bz2 yosys-a3b9692a68e88bbe3e32e0dbbd30c5e20f3800b7.zip | |
Fixed mapping of Verific WIDE_DFFRS operator
Diffstat (limited to 'frontends/verific/verific.cc')
| -rw-r--r-- | frontends/verific/verific.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index cf72b7819..7411e9434 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -466,9 +466,9 @@ static bool import_netlist_instance_cells(RTLIL::Module *module, std::map<Net*, if (inst->Type() == OPER_WIDE_DFFRS) { RTLIL::SigSpec sig_set = operatorInport(inst, "set", net_map); RTLIL::SigSpec sig_reset = operatorInport(inst, "reset", net_map); - if (sig_set.is_fully_const() && !sig_set.as_bool() && sig_set.is_fully_const() && !sig_set.as_bool()) { + if (sig_set.is_fully_const() && !sig_set.as_bool() && sig_reset.is_fully_const() && !sig_reset.as_bool()) module->addDff(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetClock()), IN, OUT); - } else + else module->addDffsr(RTLIL::escape_id(inst->Name()), net_map.at(inst->GetClock()), sig_set, sig_reset, IN, OUT); return true; } |