diff options
| author | Clifford Wolf <clifford@clifford.at> | 2018-04-07 18:38:42 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-04-07 18:38:42 +0200 |
| commit | 617c60cea67f51c6208be47377978a58e010e8c8 (patch) | |
| tree | 5132d48cd9475e30118cc72df39d7e3b6a3a035c /frontends/verific/verific.cc | |
| parent | 0ac768f9df66d010bfc9ac264b1a3228f985a994 (diff) | |
| download | yosys-617c60cea67f51c6208be47377978a58e010e8c8.tar.gz yosys-617c60cea67f51c6208be47377978a58e010e8c8.tar.bz2 yosys-617c60cea67f51c6208be47377978a58e010e8c8.zip | |
Add PRIM_HDL_ASSERTION support to Verific importer
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verific/verific.cc')
| -rw-r--r-- | frontends/verific/verific.cc | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 8e76d8949..ee09c7523 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1258,11 +1258,27 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se continue; } - if (inst->IsPrimitive()) + if (inst->Type() == PRIM_HDL_ASSERTION) { - if (inst->Type() == PRIM_HDL_ASSERTION) - continue; + SigBit cond = net_map_at(inst->GetInput()); + + if (verific_verbose) + log(" assert condition %s.\n", log_signal(cond)); + + const char *assume_attr = nullptr; // inst->GetAttValue("assume"); + + Cell *cell = nullptr; + if (assume_attr != nullptr && !strcmp(assume_attr, "1")) + cell = module->addAssume(NEW_ID, cond, State::S1); + else + cell = module->addAssert(NEW_ID, cond, State::S1); + + import_attributes(cell->attributes, inst); + continue; + } + if (inst->IsPrimitive()) + { if (!mode_keep) log_error("Unsupported Verific primitive %s of type %s\n", inst->Name(), inst->View()->Owner()->Name()); |