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| author | Clifford Wolf <clifford@clifford.at> | 2019-01-02 15:05:23 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-01-02 15:05:23 +0100 |
| commit | 50b09de03320843660636c663629c649ab242321 (patch) | |
| tree | 94b0780ce0f51c12648524e151bf45d3fa391010 /frontends/verific/verific.cc | |
| parent | 16bb823db8116ea2da2c659f8b9b2e9e2b9f2fbf (diff) | |
| download | yosys-50b09de03320843660636c663629c649ab242321.tar.gz yosys-50b09de03320843660636c663629c649ab242321.tar.bz2 yosys-50b09de03320843660636c663629c649ab242321.zip | |
Fix VerificImporter asymmetric memories error message
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/verific/verific.cc')
| -rw-r--r-- | frontends/verific/verific.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 61d9d593c..5280a2b9c 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1201,7 +1201,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se { RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetOutput()->Name())); if (memory->width != int(inst->Input2Size())) - log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name()); + log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetOutput()->Name()); RTLIL::SigSpec addr = operatorInput1(inst); RTLIL::SigSpec data = operatorInput2(inst); |