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| author | Clifford Wolf <clifford@clifford.at> | 2017-07-21 19:32:31 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2017-07-21 19:32:31 +0200 |
| commit | b3bc7068d1683cc0ac0b21cacdfb07867a7eeadb (patch) | |
| tree | 6479759cc374b0306b812f90db1a754ff52f1ec6 /frontends/verific/README | |
| parent | 36cf18ac4c1f96cad795032c3597abf08af6a6d8 (diff) | |
| download | yosys-b3bc7068d1683cc0ac0b21cacdfb07867a7eeadb.tar.gz yosys-b3bc7068d1683cc0ac0b21cacdfb07867a7eeadb.tar.bz2 yosys-b3bc7068d1683cc0ac0b21cacdfb07867a7eeadb.zip | |
Fix handling of empty cell port assignments (i.e. ignore them)
Diffstat (limited to 'frontends/verific/README')
0 files changed, 0 insertions, 0 deletions