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| author | Clifford Wolf <clifford@clifford.at> | 2019-10-24 12:13:37 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-10-24 12:13:50 +0200 |
| commit | 84982b308343315c889d3d00116db820a51cad78 (patch) | |
| tree | 9eabe561c9a24e57bddff83886e996c015bd3e3c /frontends/json | |
| parent | 34dadd9ab20494057c1ac7dae443b48eee0c2c30 (diff) | |
| download | yosys-84982b308343315c889d3d00116db820a51cad78.tar.gz yosys-84982b308343315c889d3d00116db820a51cad78.tar.bz2 yosys-84982b308343315c889d3d00116db820a51cad78.zip | |
Improve naming scheme for (VHDL) modules imported from Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/json')
0 files changed, 0 insertions, 0 deletions