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author | Clifford Wolf <clifford@clifford.at> | 2013-11-06 21:16:54 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-11-06 21:16:54 +0100 |
commit | baeca48a240928d34c357c2f8a52d392236276de (patch) | |
tree | accbb462559bd86f709cc6d74e8254ad1b4ec35f /frontends/ast | |
parent | 6fcbc79b5c53c85dfbf37eba6ef8d8b3f7f7b1c7 (diff) | |
download | yosys-baeca48a240928d34c357c2f8a52d392236276de.tar.gz yosys-baeca48a240928d34c357c2f8a52d392236276de.tar.bz2 yosys-baeca48a240928d34c357c2f8a52d392236276de.zip |
Additional fixes for undef propagation in concat and replicate ops
Diffstat (limited to 'frontends/ast')
-rw-r--r-- | frontends/ast/genrtlil.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index d32b44347..f3ca0c787 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -966,6 +966,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) sig.width += s.chunks[i].width; } } + if (sig.width < width_hint) + sig.extend(width_hint, false); return sig; } @@ -979,6 +981,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::SigSpec sig; for (int i = 0; i < count; i++) sig.append(right); + if (sig.width < width_hint) + sig.extend(width_hint, false); is_signed = false; return sig; } |