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| author | Clifford Wolf <clifford@clifford.at> | 2013-06-10 13:19:04 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-06-10 13:19:04 +0200 |
| commit | db98a18edb02a5c3a0c3f26efec0e01f8232790a (patch) | |
| tree | 2f1d2758fe775d7d39b0a09561525681f9c6452f /frontends/ast/simplify.cc | |
| parent | af79b4bd9827ec0c8aff284a44e861ab0d0efff1 (diff) | |
| download | yosys-db98a18edb02a5c3a0c3f26efec0e01f8232790a.tar.gz yosys-db98a18edb02a5c3a0c3f26efec0e01f8232790a.tar.bz2 yosys-db98a18edb02a5c3a0c3f26efec0e01f8232790a.zip | |
Enabled AST/Verilog front-end optimizations per default
Diffstat (limited to 'frontends/ast/simplify.cc')
| -rw-r--r-- | frontends/ast/simplify.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index bf0f9e63f..9035d5478 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -797,7 +797,7 @@ skip_dynamic_range_lvalue_expansion:; if (0) { case AST_REDUCE_XOR: const_func = RTLIL::const_reduce_xor; } if (0) { case AST_REDUCE_XNOR: const_func = RTLIL::const_reduce_xnor; } if (0) { case AST_REDUCE_BOOL: const_func = RTLIL::const_reduce_bool; } - if (children[0]->type == AST_CONSTANT && children[1]->type == AST_CONSTANT) { + if (children[0]->type == AST_CONSTANT) { RTLIL::Const y = const_func(RTLIL::Const(children[0]->bits), dummy_arg, children[0]->is_signed, false, -1); newNode = mkconst_bits(y.bits, false); } |