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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-18 16:01:22 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-12-18 16:01:22 +0100 |
| commit | 3d671630e2bf78cd53ef1b678a1bbb63338cbcd2 (patch) | |
| tree | 8345c80d08d31c0f21b5b608340980b3c8af4189 /frontends/ast/simplify.cc | |
| parent | 847fd360773d72933f1c728dba0755e0033350a6 (diff) | |
| download | yosys-3d671630e2bf78cd53ef1b678a1bbb63338cbcd2.tar.gz yosys-3d671630e2bf78cd53ef1b678a1bbb63338cbcd2.tar.bz2 yosys-3d671630e2bf78cd53ef1b678a1bbb63338cbcd2.zip | |
Improve src tagging (using names and attrs) of cells and wires in verific front-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/ast/simplify.cc')
0 files changed, 0 insertions, 0 deletions