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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-23 15:46:40 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-23 21:36:59 +0200 |
| commit | 71c38d9de527e1a8b55ba295df459fbcf2a0fe47 (patch) | |
| tree | a51313b07ad0f5029792760cf7a12789a5d97a18 /frontends/ast/genrtlil.cc | |
| parent | 634482380cfe5d6a1c801af0ce04e8048c5c9baf (diff) | |
| download | yosys-71c38d9de527e1a8b55ba295df459fbcf2a0fe47.tar.gz yosys-71c38d9de527e1a8b55ba295df459fbcf2a0fe47.tar.bz2 yosys-71c38d9de527e1a8b55ba295df459fbcf2a0fe47.zip | |
Add $specrule cells for $setup/$hold/$skew specify rules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index b2a22b49a..48bd466e6 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1538,6 +1538,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) cell->setParam("\\SRC_WIDTH", Const(src_width)); cell->setParam("\\DST_WIDTH", Const(dst_width)); } + if (cell->type == "$specrule") { + int src_width = GetSize(cell->getPort("\\SRC")); + int dst_width = GetSize(cell->getPort("\\DST")); + cell->setParam("\\SRC_WIDTH", Const(src_width)); + cell->setParam("\\DST_WIDTH", Const(dst_width)); + } } break; |