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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2020-04-16 12:24:04 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-05-07 21:03:13 +0200 |
| commit | 5b779f7f4ef0bf2c4ad3a412da24fad30b078626 (patch) | |
| tree | cb0fcd56575efe8a846fbd6a2888aee80998f644 /frontends/ast/genrtlil.cc | |
| parent | 06104249406972de01d0360df63a32cafcdf2ec5 (diff) | |
| download | yosys-5b779f7f4ef0bf2c4ad3a412da24fad30b078626.tar.gz yosys-5b779f7f4ef0bf2c4ad3a412da24fad30b078626.tar.bz2 yosys-5b779f7f4ef0bf2c4ad3a412da24fad30b078626.zip | |
intel_alm: direct LUTRAM cell instantiation
By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.
While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
Diffstat (limited to 'frontends/ast/genrtlil.cc')
0 files changed, 0 insertions, 0 deletions