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| author | Clifford Wolf <clifford@clifford.at> | 2019-10-14 16:49:15 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-14 16:49:15 +0200 |
| commit | 2daa56859f51631992cc172ccddad55e741b0c3d (patch) | |
| tree | ead6747321cd878dbba0543ef2e07ec02fc7a7ab /frontends/ast/genrtlil.cc | |
| parent | e909f29ca32f29352b8e05518bca1d181808e524 (diff) | |
| parent | e84cedfae4211244da45ef51a84213874579117e (diff) | |
| download | yosys-2daa56859f51631992cc172ccddad55e741b0c3d.tar.gz yosys-2daa56859f51631992cc172ccddad55e741b0c3d.tar.bz2 yosys-2daa56859f51631992cc172ccddad55e741b0c3d.zip | |
Merge pull request #1448 from YosysHQ/daveshah1-sv-experiments
Typedef support (with wrong syntax)
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 407a34472..94f5c0a04 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -863,6 +863,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_PACKAGE: case AST_MODPORT: case AST_MODPORTMEMBER: + case AST_TYPEDEF: break; case AST_INTERFACEPORT: { // If a port in a module with unknown type is found, mark it with the attribute 'is_interface' |