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authorMiodrag Milanović <mmicko@gmail.com>2019-10-18 10:52:50 +0200
committerGitHub <noreply@github.com>2019-10-18 10:52:50 +0200
commit0b0b0cc0d9e432f14218bb9ed643af3d06ab43dc (patch)
tree24f6a3cd2c4fa19a41d90cd57b0908b668efeb21 /frontends/ast/genrtlil.cc
parent0d60902fd97bba4f231f8f600434b8a69562ffff (diff)
parente0a67fce12647b4db7125d33264847c0a3781105 (diff)
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Merge branch 'master' into eddie/pr1352
Diffstat (limited to 'frontends/ast/genrtlil.cc')
-rw-r--r--frontends/ast/genrtlil.cc1
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 407a34472..94f5c0a04 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -863,6 +863,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_PACKAGE:
case AST_MODPORT:
case AST_MODPORTMEMBER:
+ case AST_TYPEDEF:
break;
case AST_INTERFACEPORT: {
// If a port in a module with unknown type is found, mark it with the attribute 'is_interface'