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author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-04-01 11:09:12 -0700 |
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committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-04-01 11:09:12 -0700 |
commit | b8dfda876795dbf08bec49ab06ac8603025d2114 (patch) | |
tree | 35cd5485c70c17e93426d54a104018bae90ed924 /frontends/ast/ast.h | |
parent | 6d2ea6fe5563205c0f565810d615c4900d4508d8 (diff) | |
parent | 22035c20ff071ec5c30990258850ecf97de5d5b3 (diff) | |
download | yosys-b8dfda876795dbf08bec49ab06ac8603025d2114.tar.gz yosys-b8dfda876795dbf08bec49ab06ac8603025d2114.tar.bz2 yosys-b8dfda876795dbf08bec49ab06ac8603025d2114.zip |
Merge remote-tracking branch 'upstream/master'
Diffstat (limited to 'frontends/ast/ast.h')
-rw-r--r-- | frontends/ast/ast.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 8b185ff51..ddd59d4be 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -282,7 +282,7 @@ namespace AST }; // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code - void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit, + void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire); // parametric modules are supported directly by the AST library |