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authorEddie Hung <eddie@fpgeh.com>2019-07-10 18:56:50 -0700
committerEddie Hung <eddie@fpgeh.com>2019-07-10 18:56:50 -0700
commitf8f0ffe786eabd016e0f9a0e4f4de10743638cdf (patch)
tree533734de284e7508b5f15a5933dd144e4446c736 /frontends/aiger
parent4a995c5d80735baf1431a088c2faf81eb75fdaf6 (diff)
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Small opt
Diffstat (limited to 'frontends/aiger')
-rw-r--r--frontends/aiger/aigerparse.cc3
1 files changed, 1 insertions, 2 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 11c5e3570..b599160cf 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -749,7 +749,6 @@ void AigerReader::post_process()
log_assert(box_module);
RTLIL::Module* flop_module = nullptr;
- const RTLIL::IdString flop_past_q = RTLIL::escape_id("\\$pastQ");
if (seen_boxes.insert(cell->type).second) {
auto it = box_module->attributes.find("\\abc_flop");
if (it != box_module->attributes.end()) {
@@ -830,7 +829,7 @@ void AigerReader::post_process()
rhs.append(wire);
}
- if (!flop_module || port_name != flop_past_q)
+ if (!flop_module || port_name != "\\$pastQ")
cell->setPort(port_name, rhs);
}