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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-08 07:58:33 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-08 07:58:33 -0700 |
| commit | ac2fc3a144fe1094bedcc6b3fda8a498ad43ae76 (patch) | |
| tree | 9ae14fabe60d01f2f13a87e905f41adbec7512c7 /frontends/aiger | |
| parent | 61d7f1997ba7e3098acc25694accdd0ff25b8ab1 (diff) | |
| parent | f69410daaf68cd3cef5e365df9b27c623ce589a7 (diff) | |
| download | yosys-ac2fc3a144fe1094bedcc6b3fda8a498ad43ae76.tar.gz yosys-ac2fc3a144fe1094bedcc6b3fda8a498ad43ae76.tar.bz2 yosys-ac2fc3a144fe1094bedcc6b3fda8a498ad43ae76.zip | |
Merge pull request #1264 from YosysHQ/eddie/fix_1254
opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)
Diffstat (limited to 'frontends/aiger')
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