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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-11 10:52:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-11 10:52:45 -0700 |
| commit | a314565ad448c1d5a76604bbd25ac2c901c08f8f (patch) | |
| tree | b23bac5198508871314acc40b936c590851987b8 /frontends/aiger | |
| parent | 8fef4c359419998eb4b068b019cbeb7faae331b7 (diff) | |
| download | yosys-a314565ad448c1d5a76604bbd25ac2c901c08f8f.tar.gz yosys-a314565ad448c1d5a76604bbd25ac2c901c08f8f.tar.bz2 yosys-a314565ad448c1d5a76604bbd25ac2c901c08f8f.zip | |
Short out async box
Diffstat (limited to 'frontends/aiger')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 77ef75cd5..b984e846a 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -741,6 +741,9 @@ void AigerReader::parse_aiger_binary() void AigerReader::post_process() { + const RTLIL::Wire* n0 = module->wire("\\__0__"); + const RTLIL::Wire* n1 = module->wire("\\__1__"); + pool<IdString> seen_boxes; dict<IdString, RTLIL::Module*> flop_data; unsigned ci_count = 0, co_count = 0, flop_count = 0; @@ -847,6 +850,17 @@ void AigerReader::post_process() flop_count++; cell->type = flop_module->name; module->connect(q, d); + continue; + } + + // Remove the async mux by shorting out its input and output + if (cell->type == "$__ABC_ASYNC") { + RTLIL::Wire* A = cell->getPort("\\A").as_wire(); + if (A == n0 || A == n1) A = nullptr; + auto it = cell->connections_.find("\\Y"); + log_assert(it != cell->connections_.end()); + module->connect(it->second, A); + cell->connections_.erase(it); } } |