Refactor for one "abc_carry" attribute on module

1 files changed, 37 insertions, 31 deletions

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 43337f4c2..7008d0542 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -732,44 +732,50 @@ void AigerReader::parse_aiger_binary()
 
 void AigerReader::post_process()
 {
-	pool<RTLIL::Module*> abc_carry_modules;
+	pool<IdString> seen_boxes;
 	unsigned ci_count = 0, co_count = 0;
 	for (auto cell : boxes) {
 		RTLIL::Module* box_module = design->module(cell->type);
 		log_assert(box_module);
 
-		if (box_module->attributes.count("\\abc_carry") && !abc_carry_modules.count(box_module)) {
-			RTLIL::Wire* carry_in = nullptr, *carry_out = nullptr;
-			RTLIL::Wire* last_in = nullptr, *last_out = nullptr;
-			for (const auto &port_name : box_module->ports) {
-				RTLIL::Wire* w = box_module->wire(port_name);
-				log_assert(w);
-				if (w->port_input) {
-					if (w->attributes.count("\\abc_carry_in")) {
-						log_assert(!carry_in);
-						carry_in = w;
-					}
-					log_assert(!last_in || last_in->port_id < w->port_id);
-					last_in = w;
-				}
-				if (w->port_output) {
-					if (w->attributes.count("\\abc_carry_out")) {
-						log_assert(!carry_out);
-						carry_out = w;
+		if (seen_boxes.insert(cell->type).second) {
+			auto it = box_module->attributes.find("\\abc_carry");
+			if (it != box_module->attributes.end()) {
+				RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
+				auto carry_in_out = it->second.decode_string();
+				auto pos = carry_in_out.find(',');
+				if (pos == std::string::npos)
+					log_error("'abc_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type));
+				auto carry_in_name = RTLIL::escape_id(carry_in_out.substr(0, pos));
+				carry_in = box_module->wire(carry_in_name);
+				if (!carry_in || !carry_in->port_input)
+					log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str());
+
+				auto carry_out_name = RTLIL::escape_id(carry_in_out.substr(pos+1));
+				carry_out = box_module->wire(carry_out_name);
+				if (!carry_out || !carry_out->port_output)
+					log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str());
+
+				auto &ports = box_module->ports;
+				for (auto jt = ports.begin(); jt != ports.end(); ) {
+					RTLIL::Wire* w = box_module->wire(*jt);
+					log_assert(w);
+					if (w == carry_in || w == carry_out) {
+						jt = ports.erase(jt);
+						continue;
 					}
-					log_assert(!last_out || last_out->port_id < w->port_id);
-					last_out = w;
+					if (w->port_id > carry_in->port_id)
+						--w->port_id;
+					if (w->port_id > carry_out->port_id)
+						--w->port_id;
+					log_assert(w->port_input || w->port_output);
+					log_assert(ports[w->port_id-1] == w->name);
+					++jt;
 				}
-			}
-
-			if (carry_in != last_in) {
-				std::swap(box_module->ports[carry_in->port_id], box_module->ports[last_in->port_id]);
-				std::swap(carry_in->port_id, last_in->port_id);
-			}
-			if (carry_out != last_out) {
-				log_assert(last_out);
-				std::swap(box_module->ports[carry_out->port_id], box_module->ports[last_out->port_id]);
-				std::swap(carry_out->port_id, last_out->port_id);
+				ports.push_back(carry_in->name);
+				carry_in->port_id = ports.size();
+				ports.push_back(carry_out->name);
+				carry_out->port_id = ports.size();
 			}
 		}