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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-21 11:16:50 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-21 11:16:50 -0800 |
| commit | 7f728bc116dc804cd944744bbc64ca155028aa22 (patch) | |
| tree | 5163b6c410a58d14f83223dc4e8e1dffe3c3a002 /frontends/aiger | |
| parent | cd8f55a91100b8dcf8b4775803cbacf70f5a998c (diff) | |
| download | yosys-7f728bc116dc804cd944744bbc64ca155028aa22.tar.gz yosys-7f728bc116dc804cd944744bbc64ca155028aa22.tar.bz2 yosys-7f728bc116dc804cd944744bbc64ca155028aa22.zip | |
read_aiger: ignore constant inputs on LUTs
Diffstat (limited to 'frontends/aiger')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index b5c861936..52bcfa0b6 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -414,6 +414,10 @@ void AigerReader::parse_xaiger() for (unsigned j = 0; j < cutLeavesM; ++j) { nodeID = parse_xaiger_literal(f); log_debug2("\t%u\n", nodeID); + if (nodeID < 2) { + log_debug("\tLUT '$lut$aiger%d$%d' input %d is constant!\n", aiger_autoidx, rootNodeID, cutLeavesM); + continue; + } RTLIL::Wire *wire = module->wire(stringf("$aiger%d$%d", aiger_autoidx, nodeID)); log_assert(wire); input_sig.append(wire); @@ -421,10 +425,10 @@ void AigerReader::parse_xaiger() // TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size()) ce.clear(); ce.compute_deps(output_sig, input_sig.to_sigbit_pool()); - RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << input_sig.size()); - for (int j = 0; j < (1 << cutLeavesM); ++j) { + RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << GetSize(input_sig)); + for (int j = 0; j < GetSize(lut_mask); ++j) { int gray = j ^ (j >> 1); - ce.set_incremental(input_sig, RTLIL::Const{gray, static_cast<int>(cutLeavesM)}); + ce.set_incremental(input_sig, RTLIL::Const{gray, GetSize(input_sig)}); RTLIL::SigBit o(output_sig); bool success YS_ATTRIBUTE(unused) = ce.eval(o); log_assert(success); |