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authorEddie Hung <eddieh@ece.ubc.ca>2019-02-08 12:40:43 -0800
committerEddie Hung <eddieh@ece.ubc.ca>2019-02-08 12:40:43 -0800
commitfb8ad440a32da850e32765ec29119cacb3f3c27c (patch)
tree7a0ffe0f8b72e0cd4911b0d676bab35e23df116a /frontends/aiger/aigerparse.h
parentf1befe1b44ada400e979f43e1b35ebe022ff8fe8 (diff)
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Allow module name to be determined by argument too
Diffstat (limited to 'frontends/aiger/aigerparse.h')
-rw-r--r--frontends/aiger/aigerparse.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h
index 3e8ef09fc..39a77bd93 100644
--- a/frontends/aiger/aigerparse.h
+++ b/frontends/aiger/aigerparse.h
@@ -28,7 +28,7 @@ struct AigerReader
{
RTLIL::Design *design;
std::istream &f;
- std::string clk_name;
+ RTLIL::IdString clk_name;
RTLIL::Module *module;
unsigned M, I, L, O, A;
@@ -39,7 +39,7 @@ struct AigerReader
std::vector<RTLIL::Wire*> latches;
std::vector<RTLIL::Wire*> outputs;
- AigerReader(RTLIL::Design *design, std::istream &f, std::string clk_name="clk");
+ AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name);
void parse_aiger();
void parse_aiger_ascii();
void parse_aiger_binary();