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| author | Clifford Wolf <clifford@clifford.at> | 2018-02-23 13:14:47 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-02-23 13:14:47 +0100 |
| commit | eb67a7532bf1d8195216257a2d6d301c03980591 (patch) | |
| tree | f9246e5ace86c1cc365b4f5111061d99fbcc9aeb /examples | |
| parent | 2521ed305e9d48929c9ede93b8cb0069739408f5 (diff) | |
| download | yosys-eb67a7532bf1d8195216257a2d6d301c03980591.tar.gz yosys-eb67a7532bf1d8195216257a2d6d301c03980591.tar.bz2 yosys-eb67a7532bf1d8195216257a2d6d301c03980591.zip | |
Add $allconst and $allseq cell types
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'examples')
| -rw-r--r-- | examples/smtbmc/demo2.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/examples/smtbmc/demo2.v b/examples/smtbmc/demo2.v index 34745e898..0cf529a42 100644 --- a/examples/smtbmc/demo2.v +++ b/examples/smtbmc/demo2.v @@ -9,7 +9,7 @@ module demo2(input clk, input [4:0] addr, output reg [31:0] data); reg [31:0] mem [0:31]; - always @(posedge clk) + always @(negedge clk) data <= mem[addr]; reg [31:0] used_addr = 0; |