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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-27 10:19:27 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-27 10:19:27 -0700 |
| commit | eab3c1432b717bb341773878bf0daece7d39dec8 (patch) | |
| tree | e30aa036be3c84d29f357e2faa015190ec8e195c /examples | |
| parent | fdbcf789099d327bd5e9f2e0658cdad754b09db2 (diff) | |
| parent | 5fb4b12cb50b870b546d76f9c702678d8f0aa60a (diff) | |
| download | yosys-eab3c1432b717bb341773878bf0daece7d39dec8.tar.gz yosys-eab3c1432b717bb341773878bf0daece7d39dec8.tar.bz2 yosys-eab3c1432b717bb341773878bf0daece7d39dec8.zip | |
Merge pull request #1292 from YosysHQ/mwk/xilinx_bufgmap
Add clock buffer insertion pass, improve iopadmap.
Diffstat (limited to 'examples')
| -rw-r--r-- | examples/mimas2/run_yosys.ys | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/examples/mimas2/run_yosys.ys b/examples/mimas2/run_yosys.ys index b3204b1ca..b48877811 100644 --- a/examples/mimas2/run_yosys.ys +++ b/examples/mimas2/run_yosys.ys @@ -1,4 +1,3 @@ read_verilog example.v -synth_xilinx -top example -family xc6s -iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I +synth_xilinx -top example -family xc6s -ise write_edif -pvector bra example.edif |