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| author | whitequark <whitequark@whitequark.org> | 2019-12-04 11:59:36 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2019-12-04 11:59:36 +0000 |
| commit | e97e33d00df9d702643a82152aa1becc611ef823 (patch) | |
| tree | d6a56f374db5ee9dda0fb6af63cc7dd932106c65 /examples | |
| parent | ec4c9267b384030b487e66a77e4cc4ef600e876f (diff) | |
| download | yosys-e97e33d00df9d702643a82152aa1becc611ef823.tar.gz yosys-e97e33d00df9d702643a82152aa1becc611ef823.tar.bz2 yosys-e97e33d00df9d702643a82152aa1becc611ef823.zip | |
kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.
Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.
Also fix the Verilog frontend to never emit such constructs.
Diffstat (limited to 'examples')
0 files changed, 0 insertions, 0 deletions