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| author | Clifford Wolf <clifford@clifford.at> | 2019-01-17 14:38:37 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-01-17 14:38:37 +0100 |
| commit | db5765b443c26b5b2dc3ac56d5a448fc8b861d43 (patch) | |
| tree | 1d618cc08ef5a17d11feee182604f527848a1ad6 /examples | |
| parent | 9b277fc21ea455a0e0ca9b7acde039e90ddb380d (diff) | |
| download | yosys-db5765b443c26b5b2dc3ac56d5a448fc8b861d43.tar.gz yosys-db5765b443c26b5b2dc3ac56d5a448fc8b861d43.tar.bz2 yosys-db5765b443c26b5b2dc3ac56d5a448fc8b861d43.zip | |
Add SF2 IO buffer insertion
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'examples')
| -rw-r--r-- | examples/igloo2/example.v | 3 | ||||
| -rw-r--r-- | examples/igloo2/libero.tcl | 2 |
2 files changed, 3 insertions, 2 deletions
diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v index 0e336e557..1a1967d5a 100644 --- a/examples/igloo2/example.v +++ b/examples/igloo2/example.v @@ -1,5 +1,6 @@ module example ( input clk, + input EN, output LED1, output LED2, output LED3, @@ -14,7 +15,7 @@ module example ( reg [BITS-1:0] outcnt; always @(posedge clk) begin - counter <= counter + 1; + counter <= counter + EN; outcnt <= counter >> LOG2DELAY; end diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl index b2090f402..952342a4c 100644 --- a/examples/igloo2/libero.tcl +++ b/examples/igloo2/libero.tcl @@ -5,7 +5,7 @@ file delete -force proj new_project \ -name example \ -location proj \ - -block_mode 1 \ + -block_mode 0 \ -hdl "VERILOG" \ -family IGLOO2 \ -die PA4MGL500 \ |