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author | Clifford Wolf <clifford@clifford.at> | 2016-10-14 15:24:03 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2016-10-14 15:24:03 +0200 |
commit | bdc316db50cd8b68ef096386a89c1b38793784e1 (patch) | |
tree | 507341053afa28df1a753ef9de33c3d096683720 /examples | |
parent | 2733994aeba0879533cc1a871aae84497b32ff9e (diff) | |
download | yosys-bdc316db50cd8b68ef096386a89c1b38793784e1.tar.gz yosys-bdc316db50cd8b68ef096386a89c1b38793784e1.tar.bz2 yosys-bdc316db50cd8b68ef096386a89c1b38793784e1.zip |
Added $anyseq cell type
Diffstat (limited to 'examples')
-rw-r--r-- | examples/smtbmc/demo7.v | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/examples/smtbmc/demo7.v b/examples/smtbmc/demo7.v index 75b3865c5..63f6272f1 100644 --- a/examples/smtbmc/demo7.v +++ b/examples/smtbmc/demo7.v @@ -1,6 +1,7 @@ // Demo for memory initialization -module demo7 (input [2:0] addr); +module demo7; + wire [2:0] addr = $anyseq; reg [15:0] memory [0:7]; initial begin |