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| author | Clifford Wolf <clifford@clifford.at> | 2018-05-30 14:17:36 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-05-30 14:17:36 +0200 |
| commit | 7f0548c16f64bd0c4e3bd85744cfdcf9494b4829 (patch) | |
| tree | 9ca6fdebbd47f6793edace0106805a6c7235c37a /examples | |
| parent | 7fecc3c199e6cfe4b474431d54027d699bc8d343 (diff) | |
| download | yosys-7f0548c16f64bd0c4e3bd85744cfdcf9494b4829.tar.gz yosys-7f0548c16f64bd0c4e3bd85744cfdcf9494b4829.tar.bz2 yosys-7f0548c16f64bd0c4e3bd85744cfdcf9494b4829.zip | |
Update examples/cmos/counter.ys to use "synth" command
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'examples')
| -rw-r--r-- | examples/cmos/counter.ys | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/examples/cmos/counter.ys b/examples/cmos/counter.ys index a784f3465..d0b093667 100644 --- a/examples/cmos/counter.ys +++ b/examples/cmos/counter.ys @@ -1,11 +1,12 @@ - read_verilog counter.v read_verilog -lib cmos_cells.v -proc;; memory;; techmap;; - +synth dfflibmap -liberty cmos_cells.lib -abc -liberty cmos_cells.lib;; +abc -liberty cmos_cells.lib +opt_clean + +stat -liberty cmos_cells.lib # http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib # dfflibmap -liberty osu025_stdcells.lib @@ -13,4 +14,3 @@ abc -liberty cmos_cells.lib;; write_verilog synth.v write_spice synth.sp - |