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| author | whitequark <whitequark@whitequark.org> | 2018-12-21 02:01:27 +0000 |
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| committer | whitequark <whitequark@whitequark.org> | 2018-12-21 02:01:27 +0000 |
| commit | 0c318e7db513bed1844f594ae780f854ed08e18f (patch) | |
| tree | 31804c863f66c2231db22f99855f02487bbeb2fa /examples | |
| parent | 93d44bb9a613b46a80642b8ce71295db18fadbc5 (diff) | |
| download | yosys-0c318e7db513bed1844f594ae780f854ed08e18f.tar.gz yosys-0c318e7db513bed1844f594ae780f854ed08e18f.tar.bz2 yosys-0c318e7db513bed1844f594ae780f854ed08e18f.zip | |
memory_collect: do not truncate 'x from \INIT.
The semantics of an RTLIL constant that has less bits than its
declared bit width is zero padding. Therefore, if the output of
memory_collect will be used for simulation, truncating 'x from
the end of \INIT will produce incorrect simulation results.
Diffstat (limited to 'examples')
0 files changed, 0 insertions, 0 deletions