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authorEddie Hung <eddie@fpgeh.com>2019-08-28 12:18:32 -0700
committerEddie Hung <eddie@fpgeh.com>2019-08-28 12:18:32 -0700
commit32eef26ee277b79736e135a8800625543dd6080a (patch)
tree28cd6d5af904ddd2ec2772e2bd1d2378215c1dc7 /examples/mimas2/run_yosys.ys
parentfe58790f3789a79b867660031d7e3e28cb3fff20 (diff)
parentc499dc3e73390c3bc9bf8045f2e4cad963c1fbad (diff)
downloadyosys-32eef26ee277b79736e135a8800625543dd6080a.tar.gz
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Merge remote-tracking branch 'origin/clifford/async2synclatch' into Sergey/tests_ice40
Diffstat (limited to 'examples/mimas2/run_yosys.ys')
-rw-r--r--examples/mimas2/run_yosys.ys3
1 files changed, 1 insertions, 2 deletions
diff --git a/examples/mimas2/run_yosys.ys b/examples/mimas2/run_yosys.ys
index b3204b1ca..b48877811 100644
--- a/examples/mimas2/run_yosys.ys
+++ b/examples/mimas2/run_yosys.ys
@@ -1,4 +1,3 @@
read_verilog example.v
-synth_xilinx -top example -family xc6s
-iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I
+synth_xilinx -top example -family xc6s -ise
write_edif -pvector bra example.edif