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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-04-12 11:52:45 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-12 11:52:45 -0700 |
| commit | db1a5ec6a2a437b296e7ba9de78afaf3b440327f (patch) | |
| tree | c69ad0ec722306598fff9040ccb06acac75b625f /examples/intel | |
| parent | 9d6586b4e131b058dc4fddf9d9d44968887af91b (diff) | |
| parent | 1f9235ede5d5fee4ce0ad13c2905f624e9493426 (diff) | |
| download | yosys-db1a5ec6a2a437b296e7ba9de78afaf3b440327f.tar.gz yosys-db1a5ec6a2a437b296e7ba9de78afaf3b440327f.tar.bz2 yosys-db1a5ec6a2a437b296e7ba9de78afaf3b440327f.zip | |
Merge pull request #928 from litghost/add_xc7_sim_models
Add additional cells sim models for core 7-series primitives.
Diffstat (limited to 'examples/intel')
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