aboutsummaryrefslogtreecommitdiffstats
path: root/examples/igloo2
diff options
context:
space:
mode:
authorClifford Wolf <clifford@clifford.at>2019-03-05 17:27:58 -0800
committerClifford Wolf <clifford@clifford.at>2019-03-05 17:27:58 -0800
commit24d1b92eda20269da7ee7ae713f3ab92b8865349 (patch)
treee6c1595d922f1f2018f7d40b8002641e5b4298ff /examples/igloo2
parentbfcd46dbd30f75aabfbfd8439819c4f7fe17adc8 (diff)
downloadyosys-24d1b92eda20269da7ee7ae713f3ab92b8865349.tar.gz
yosys-24d1b92eda20269da7ee7ae713f3ab92b8865349.tar.bz2
yosys-24d1b92eda20269da7ee7ae713f3ab92b8865349.zip
Improve igloo2 exmaple
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'examples/igloo2')
-rw-r--r--examples/igloo2/example.pdc7
-rw-r--r--examples/igloo2/example.sdc1
-rw-r--r--examples/igloo2/example.v12
-rw-r--r--examples/igloo2/libero.tcl4
4 files changed, 16 insertions, 8 deletions
diff --git a/examples/igloo2/example.pdc b/examples/igloo2/example.pdc
index e6ffd53db..0cf34adb3 100644
--- a/examples/igloo2/example.pdc
+++ b/examples/igloo2/example.pdc
@@ -1 +1,8 @@
# Add placement constraints here
+set_io clk -pinname H16 -fixed yes -DIRECTION INPUT
+set_io SW1 -pinname H12 -fixed yes -DIRECTION INPUT
+set_io SW2 -pinname H13 -fixed yes -DIRECTION INPUT
+set_io LED1 -pinname J16 -fixed yes -DIRECTION OUTPUT
+set_io LED2 -pinname M16 -fixed yes -DIRECTION OUTPUT
+set_io LED3 -pinname K16 -fixed yes -DIRECTION OUTPUT
+set_io LED4 -pinname N16 -fixed yes -DIRECTION OUTPUT
diff --git a/examples/igloo2/example.sdc b/examples/igloo2/example.sdc
index c6ff94161..f8b487316 100644
--- a/examples/igloo2/example.sdc
+++ b/examples/igloo2/example.sdc
@@ -1 +1,2 @@
# Add timing constraints here
+create_clock -period 10.000 -waveform {0.000 5.000} [get_ports {clk}]
diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v
index 1a1967d5a..b701c707d 100644
--- a/examples/igloo2/example.v
+++ b/examples/igloo2/example.v
@@ -1,23 +1,23 @@
module example (
input clk,
- input EN,
+ input SW1,
+ input SW2,
output LED1,
output LED2,
output LED3,
- output LED4,
- output LED5
+ output LED4
);
- localparam BITS = 5;
+ localparam BITS = 4;
localparam LOG2DELAY = 22;
reg [BITS+LOG2DELAY-1:0] counter = 0;
reg [BITS-1:0] outcnt;
always @(posedge clk) begin
- counter <= counter + EN;
+ counter <= counter + SW1 + SW2 + 1;
outcnt <= counter >> LOG2DELAY;
end
- assign {LED1, LED2, LED3, LED4, LED5} = outcnt ^ (outcnt >> 1);
+ assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1);
endmodule
diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl
index 6f7d4e24b..abc94e479 100644
--- a/examples/igloo2/libero.tcl
+++ b/examples/igloo2/libero.tcl
@@ -8,8 +8,8 @@ new_project \
-block_mode 0 \
-hdl "VERILOG" \
-family IGLOO2 \
- -die PA4MGL500 \
- -package tq144 \
+ -die PA4MGL2500 \
+ -package vf256 \
-speed -1
import_files -hdl_source {netlist.vm}