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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-22 09:01:00 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-22 09:01:00 +0200 |
| commit | cbd9b8a3f38b15874d36e5ba116536a981756411 (patch) | |
| tree | 080b5e2902cb56ce5a5a6c6c34e69d25a2819972 /examples/igloo2/example.pdc | |
| parent | 19fd411e77be57eb6b7a273b8acaa25d462186ef (diff) | |
| parent | a3371e118b05eb9bd5dddb1c20758674ae50a803 (diff) | |
| download | yosys-cbd9b8a3f38b15874d36e5ba116536a981756411.tar.gz yosys-cbd9b8a3f38b15874d36e5ba116536a981756411.tar.bz2 yosys-cbd9b8a3f38b15874d36e5ba116536a981756411.zip | |
Merge pull request #916 from YosysHQ/map_cells_before_map_luts
synth_xilinx to map_cells before map_luts
Diffstat (limited to 'examples/igloo2/example.pdc')
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