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| author | Clifford Wolf <clifford@clifford.at> | 2015-10-13 15:40:21 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-10-13 15:41:20 +0200 |
| commit | f42218682d2c7caa6caa81cb2ca48f0c3f62bb5b (patch) | |
| tree | eed220c7c84c673dec27bca4c2e96d919831f8b7 /examples/cmos/testbench.sp | |
| parent | f13e3873212fb4338ee3dd180cb9b0cd3d134935 (diff) | |
| download | yosys-f42218682d2c7caa6caa81cb2ca48f0c3f62bb5b.tar.gz yosys-f42218682d2c7caa6caa81cb2ca48f0c3f62bb5b.tar.bz2 yosys-f42218682d2c7caa6caa81cb2ca48f0c3f62bb5b.zip | |
Added examples/ top-level directory
Diffstat (limited to 'examples/cmos/testbench.sp')
| -rw-r--r-- | examples/cmos/testbench.sp | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/examples/cmos/testbench.sp b/examples/cmos/testbench.sp new file mode 100644 index 000000000..95d2f67cd --- /dev/null +++ b/examples/cmos/testbench.sp @@ -0,0 +1,29 @@ + +* supply voltages +.global Vss Vdd +Vss Vss 0 DC 0 +Vdd Vdd 0 DC 3 + +* simple transistor model +.MODEL cmosn NMOS LEVEL=1 VT0=0.7 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7 +.MODEL cmosp PMOS LEVEL=1 VT0=-0.7 KP=50U GAMMA=0.57 LAMBDA=0.05 PHI=0.8 + +* load design and library +.include synth.sp +.include cmos_cells.sp + +* input signals +Vclk clk 0 PULSE(0 3 1 0.1 0.1 0.8 2) +Vrst rst 0 PULSE(0 3 0.5 0.1 0.1 2.9 40) +Ven en 0 PULSE(0 3 0.5 0.1 0.1 5.9 8) + +Xuut clk rst en out0 out1 out2 COUNTER + +.tran 0.01 50 + +.control +run +plot v(clk) v(rst)+5 v(en)+10 v(out0)+20 v(out1)+25 v(out2)+30 +.endc + +.end |