Remove docs dependency on yosys repo (#3558)

* Copies guidelines files into docs/ for website

* Copying manual/CHAPTER_Prog for new docs

* Copying manual/APPNOTE_011... for new docs

Also adding faketime to list of packages for website build.

Co-authored-by: KrystalDelusion <krystinedawn@yosyshq.com>

37 files changed, 897 insertions, 15 deletions

diff --git a/docs/.gitignore b/docs/.gitignore
index 26645e4cb..e36f2309a 100644
--- a/docs/.gitignore
+++ b/docs/.gitignore
@@ -1,5 +1,6 @@
 /build/
 /source/cmd
+/source/temp
 /images/*.log
 /images/*.aux
 /images/*.pdf
diff --git a/docs/images/Makefile b/docs/images/Makefile
index 84e09615f..a7216ec90 100644
--- a/docs/images/Makefile
+++ b/docs/images/Makefile
@@ -1,7 +1,7 @@
 all: dots tex svg tidy
 
 TEX_SOURCE:= $(wildcard *.tex)
-DOT_LOC:= ../../manual/APPNOTE_011_Design_Investigation
+DOT_LOC:= ../source/APPNOTE_011_Design_Investigation
 DOT_SOURCE:= $(wildcard $(DOT_LOC)/*.dot)
 
 TEX_SOURCE+= 011/example_out.tex
diff --git a/docs/source/APPNOTE_011_Design_Investigation/cmos.v b/docs/source/APPNOTE_011_Design_Investigation/cmos.v
new file mode 100644
index 000000000..2912c760a
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/cmos.v
@@ -0,0 +1,3 @@
+module cmos_demo(input a, b, output [1:0] y);
+assign y = a + b;
+endmodule
diff --git a/docs/source/APPNOTE_011_Design_Investigation/cmos_00.dot b/docs/source/APPNOTE_011_Design_Investigation/cmos_00.dot
new file mode 100644
index 000000000..49c630080
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/cmos_00.dot
@@ -0,0 +1,34 @@
+digraph "cmos_demo" {
+rankdir="LR";
+remincross=true;
+n4 [ shape=octagon, label="a", color="black", fontcolor="black" ];
+n5 [ shape=octagon, label="b", color="black", fontcolor="black" ];
+n6 [ shape=octagon, label="y", color="black", fontcolor="black" ];
+c10 [ shape=record, label="{{<p7> A|<p8> B|<p9> Y}|$g0\nNOR|{}}" ];
+c11 [ shape=record, label="{{<p7> A|<p9> Y}|$g1\nNOT|{}}" ];
+c12 [ shape=record, label="{{<p7> A|<p9> Y}|$g2\nNOT|{}}" ];
+c13 [ shape=record, label="{{<p7> A|<p8> B|<p9> Y}|$g3\nNOR|{}}" ];
+x0 [ shape=record, style=rounded, label="<s0> 1:1 - 0:0 " ];
+x0:e -> c13:p9:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, color="black", label=""];
+c14 [ shape=record, label="{{<p7> A|<p8> B|<p9> Y}|$g4\nNOR|{}}" ];
+x1 [ shape=record, style=rounded, label="<s0> 1:1 - 0:0 " ];
+x1:e -> c14:p8:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, color="black", label=""];
+x2 [ shape=record, style=rounded, label="<s0> 0:0 - 0:0 " ];
+x2:e -> c14:p9:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, color="black", label=""];
+n1 [ shape=diamond, label="$n4" ];
+n1:e -> c10:p9:w [color="black", label=""];
+n1:e -> c14:p7:w [color="black", label=""];
+n2 [ shape=diamond, label="$n5" ];
+n2:e -> c11:p9:w [color="black", label=""];
+n2:e -> c13:p7:w [color="black", label=""];
+n3 [ shape=diamond, label="$n6_1" ];
+n3:e -> c12:p9:w [color="black", label=""];
+n3:e -> c13:p8:w [color="black", label=""];
+n4:e -> c10:p8:w [color="black", label=""];
+n4:e -> c12:p7:w [color="black", label=""];
+n5:e -> c10:p7:w [color="black", label=""];
+n5:e -> c11:p7:w [color="black", label=""];
+n6:e -> x0:s0:w [color="black", label=""];
+n6:e -> x1:s0:w [color="black", label=""];
+n6:e -> x2:s0:w [color="black", label=""];
+}
diff --git a/docs/source/APPNOTE_011_Design_Investigation/cmos_01.dot b/docs/source/APPNOTE_011_Design_Investigation/cmos_01.dot
new file mode 100644
index 000000000..ea6f4403c
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/cmos_01.dot
@@ -0,0 +1,23 @@
+digraph "cmos_demo" {
+rankdir="LR";
+remincross=true;
+n4 [ shape=octagon, label="a", color="black", fontcolor="black" ];
+n5 [ shape=octagon, label="b", color="black", fontcolor="black" ];
+n6 [ shape=octagon, label="y[0]", color="black", fontcolor="black" ];
+n7 [ shape=octagon, label="y[1]", color="black", fontcolor="black" ];
+c11 [ shape=record, label="{{<p8> A|<p9> B}|$g0\nNOR|{<p10> Y}}" ];
+c12 [ shape=record, label="{{<p8> A}|$g1\nNOT|{<p10> Y}}" ];
+c13 [ shape=record, label="{{<p8> A}|$g2\nNOT|{<p10> Y}}" ];
+c14 [ shape=record, label="{{<p8> A|<p9> B}|$g3\nNOR|{<p10> Y}}" ];
+c15 [ shape=record, label="{{<p8> A|<p9> B}|$g4\nNOR|{<p10> Y}}" ];
+c11:p10:e -> c15:p8:w [color="black", label=""];
+c12:p10:e -> c14:p8:w [color="black", label=""];
+c13:p10:e -> c14:p9:w [color="black", label=""];
+n4:e -> c11:p9:w [color="black", label=""];
+n4:e -> c13:p8:w [color="black", label=""];
+n5:e -> c11:p8:w [color="black", label=""];
+n5:e -> c12:p8:w [color="black", label=""];
+c15:p10:e -> n6:w [color="black", label=""];
+c14:p10:e -> n7:w [color="black", label=""];
+n7:e -> c15:p9:w [color="black", label=""];
+}
diff --git a/docs/source/APPNOTE_011_Design_Investigation/example.v b/docs/source/APPNOTE_011_Design_Investigation/example.v
new file mode 100644
index 000000000..8c71989b3
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/example.v
@@ -0,0 +1,6 @@
+module example(input clk, a, b, c,
+               output reg [1:0] y);
+    always @(posedge clk)
+        if (c)
+            y <= c ? a + b : 2'd0;
+endmodule
diff --git a/docs/source/APPNOTE_011_Design_Investigation/example.ys b/docs/source/APPNOTE_011_Design_Investigation/example.ys
new file mode 100644
index 000000000..b1e956088
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/example.ys
@@ -0,0 +1,11 @@
+read_verilog example.v
+show -format dot -prefix example_00
+proc
+show -format dot -prefix example_01
+opt
+show -format dot -prefix example_02
+
+cd example
+select t:$add
+show -format dot -prefix example_03
+
diff --git a/docs/source/APPNOTE_011_Design_Investigation/example_00.dot b/docs/source/APPNOTE_011_Design_Investigation/example_00.dot
new file mode 100644
index 000000000..1e23ed0ea
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/example_00.dot
@@ -0,0 +1,23 @@
+digraph "example" {
+rankdir="LR";
+remincross=true;
+n4 [ shape=octagon, label="a", color="black", fontcolor="black" ];
+n5 [ shape=octagon, label="b", color="black", fontcolor="black" ];
+n6 [ shape=octagon, label="c", color="black", fontcolor="black" ];
+n7 [ shape=octagon, label="clk", color="black", fontcolor="black" ];
+n8 [ shape=octagon, label="y", color="black", fontcolor="black" ];
+c12 [ shape=record, label="{{<p9> A|<p10> B}|$2\n$add|{<p11> Y}}" ];
+v0 [ label="2'00" ];
+c14 [ shape=record, label="{{<p9> A|<p10> B|<p13> S}|$3\n$mux|{<p11> Y}}" ];
+p1 [shape=box, style=rounded, label="PROC $1\nexample.v:3"];
+c12:p11:e -> c14:p10:w [color="black", style="setlinewidth(3)", label=""];
+c14:p11:e -> p1:w [color="black", style="setlinewidth(3)", label=""];
+n4:e -> c12:p9:w [color="black", label=""];
+n5:e -> c12:p10:w [color="black", label=""];
+n6:e -> c14:p13:w [color="black", label=""];
+n6:e -> p1:w [color="black", label=""];
+n7:e -> p1:w [color="black", label=""];
+p1:e -> n8:w [color="black", style="setlinewidth(3)", label=""];
+n8:e -> p1:w [color="black", style="setlinewidth(3)", label=""];
+v0:e -> c14:p9:w [color="black", style="setlinewidth(3)", label=""];
+}
diff --git a/docs/source/APPNOTE_011_Design_Investigation/example_01.dot b/docs/source/APPNOTE_011_Design_Investigation/example_01.dot
new file mode 100644
index 000000000..e89292b51
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/example_01.dot
@@ -0,0 +1,33 @@
+digraph "example" {
+rankdir="LR";
+remincross=true;
+n6 [ shape=octagon, label="a", color="black", fontcolor="black" ];
+n7 [ shape=octagon, label="b", color="black", fontcolor="black" ];
+n8 [ shape=octagon, label="c", color="black", fontcolor="black" ];
+n9 [ shape=octagon, label="clk", color="black", fontcolor="black" ];
+n10 [ shape=octagon, label="y", color="black", fontcolor="black" ];
+c14 [ shape=record, label="{{<p11> A|<p12> B}|$2\n$add|{<p13> Y}}" ];
+c18 [ shape=record, label="{{<p15> CLK|<p16> D}|$7\n$dff|{<p17> Q}}" ];
+c20 [ shape=record, label="{{<p11> A|<p12> B|<p19> S}|$5\n$mux|{<p13> Y}}" ];
+v0 [ label="2'00" ];
+c21 [ shape=record, label="{{<p11> A|<p12> B|<p19> S}|$3\n$mux|{<p13> Y}}" ];
+x1 [shape=box, style=rounded, label="BUF"];
+x2 [shape=box, style=rounded, label="BUF"];
+n1 [ shape=diamond, label="$0\\y[1:0]" ];
+x2:e:e -> n1:w [color="black", style="setlinewidth(3)", label=""];
+c18:p17:e -> n10:w [color="black", style="setlinewidth(3)", label=""];
+n10:e -> c20:p11:w [color="black", style="setlinewidth(3)", label=""];
+c14:p13:e -> c21:p12:w [color="black", style="setlinewidth(3)", label=""];
+n3 [ shape=point ];
+c20:p13:e -> n3:w [color="black", style="setlinewidth(3)", label=""];
+n3:e -> c18:p16:w [color="black", style="setlinewidth(3)", label=""];
+n3:e -> x2:w:w [color="black", style="setlinewidth(3)", label=""];
+x1:e:e -> c20:p19:w [color="black", label=""];
+c21:p13:e -> c20:p12:w [color="black", style="setlinewidth(3)", label=""];
+n6:e -> c14:p11:w [color="black", label=""];
+n7:e -> c14:p12:w [color="black", label=""];
+n8:e -> c21:p19:w [color="black", label=""];
+n8:e -> x1:w:w [color="black", label=""];
+n9:e -> c18:p15:w [color="black", label=""];
+v0:e -> c21:p11:w [color="black", style="setlinewidth(3)", label=""];
+}
diff --git a/docs/source/APPNOTE_011_Design_Investigation/example_02.dot b/docs/source/APPNOTE_011_Design_Investigation/example_02.dot
new file mode 100644
index 000000000..f950ed2ed
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/example_02.dot
@@ -0,0 +1,20 @@
+digraph "example" {
+rankdir="LR";
+remincross=true;
+n3 [ shape=octagon, label="a", color="black", fontcolor="black" ];
+n4 [ shape=octagon, label="b", color="black", fontcolor="black" ];
+n5 [ shape=octagon, label="c", color="black", fontcolor="black" ];
+n6 [ shape=octagon, label="clk", color="black", fontcolor="black" ];
+n7 [ shape=octagon, label="y", color="black", fontcolor="black" ];
+c11 [ shape=record, label="{{<p8> A|<p9> B}|$2\n$add|{<p10> Y}}" ];
+c15 [ shape=record, label="{{<p12> CLK|<p13> D}|$7\n$dff|{<p14> Q}}" ];
+c17 [ shape=record, label="{{<p8> A|<p9> B|<p16> S}|$5\n$mux|{<p10> Y}}" ];
+c17:p10:e -> c15:p13:w [color="black", style="setlinewidth(3)", label=""];
+c11:p10:e -> c17:p9:w [color="black", style="setlinewidth(3)", label=""];
+n3:e -> c11:p8:w [color="black", label=""];
+n4:e -> c11:p9:w [color="black", label=""];
+n5:e -> c17:p16:w [color="black", label=""];
+n6:e -> c15:p12:w [color="black", label=""];
+c15:p14:e -> n7:w [color="black", style="setlinewidth(3)", label=""];
+n7:e -> c17:p8:w [color="black", style="setlinewidth(3)", label=""];
+}
diff --git a/docs/source/APPNOTE_011_Design_Investigation/example_03.dot b/docs/source/APPNOTE_011_Design_Investigation/example_03.dot
new file mode 100644
index 000000000..e19d24af7
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/example_03.dot
@@ -0,0 +1,11 @@
+digraph "example" {
+rankdir="LR";
+remincross=true;
+v0 [ label="a" ];
+v1 [ label="b" ];
+v2 [ label="$2_Y" ];
+c4 [ shape=record, label="{{<p1> A|<p2> B}|$2\n$add|{<p3> Y}}" ];
+v0:e -> c4:p1:w [color="black", label=""];
+v1:e -> c4:p2:w [color="black", label=""];
+c4:p3:e -> v2:w [color="black", style="setlinewidth(3)", label=""];
+}
diff --git a/docs/source/APPNOTE_011_Design_Investigation/foobaraddsub.v b/docs/source/APPNOTE_011_Design_Investigation/foobaraddsub.v
new file mode 100644
index 000000000..0f277211d
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/foobaraddsub.v
@@ -0,0 +1,8 @@
+module foobaraddsub(a, b, c, d, fa, fs, ba, bs);
+  input [7:0] a, b, c, d;
+  output [7:0] fa, fs, ba, bs;
+  assign fa = a + (* foo *) b;
+  assign fs = a - (* foo *) b;
+  assign ba = c + (* bar *) d;
+  assign bs = c - (* bar *) d;
+endmodule
diff --git a/docs/source/APPNOTE_011_Design_Investigation/make.sh b/docs/source/APPNOTE_011_Design_Investigation/make.sh
new file mode 100644
index 000000000..3845dac6b
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/make.sh
@@ -0,0 +1,23 @@
+#!/bin/bash
+set -ex
+if false; then
+	rm -f *.dot
+	../../yosys example.ys
+	../../yosys -p 'proc; opt; show -format dot -prefix splice' splice.v
+	../../yosys -p 'techmap; abc -liberty ../../techlibs/cmos/cmos_cells.lib;; show -format dot -prefix cmos_00' cmos.v
+	../../yosys -p 'techmap; splitnets -ports; abc -liberty ../../techlibs/cmos/cmos_cells.lib;; show -lib ../../techlibs/cmos/cmos_cells.v -format dot -prefix cmos_01' cmos.v
+	../../yosys -p 'opt; cd sumprod; select a:sumstuff; show -format dot -prefix sumprod_00' sumprod.v
+	../../yosys -p 'opt; cd sumprod; select a:sumstuff %x; show -format dot -prefix sumprod_01' sumprod.v
+	../../yosys -p 'opt; cd sumprod; select prod; show -format dot -prefix sumprod_02' sumprod.v
+	../../yosys -p 'opt; cd sumprod; select prod %ci; show -format dot -prefix sumprod_03' sumprod.v
+	../../yosys -p 'opt; cd sumprod; select prod %ci2; show -format dot -prefix sumprod_04' sumprod.v
+	../../yosys -p 'opt; cd sumprod; select prod %ci3; show -format dot -prefix sumprod_05' sumprod.v
+	../../yosys -p 'proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_00' memdemo.v
+	../../yosys -p 'proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_01 y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff' memdemo.v
+	../../yosys submod.ys
+	sed -i '/^label=/ d;' *.dot
+fi
+for dot_file in *.dot; do
+	pdf_file=${dot_file%.dot}.pdf
+	dot -Tpdf -o $pdf_file $dot_file
+done
diff --git a/docs/source/APPNOTE_011_Design_Investigation/memdemo.v b/docs/source/APPNOTE_011_Design_Investigation/memdemo.v
new file mode 100644
index 000000000..b39564ddc
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/memdemo.v
@@ -0,0 +1,19 @@
+module memdemo(clk, d, y);
+
+input clk;
+input [3:0] d;
+output reg [3:0] y;
+
+integer i;
+reg [1:0] s1, s2;
+reg [3:0] mem [0:3];
+
+always @(posedge clk) begin
+    for (i = 0; i < 4; i = i+1)
+        mem[i] <= mem[(i+1) % 4] + mem[(i+2) % 4];
+    { s2, s1 } = d ? { s1, s2 } ^ d : 4'b0;
+    mem[s1] <= d;
+    y <= mem[s2];
+end
+
+endmodule
diff --git a/docs/source/APPNOTE_011_Design_Investigation/memdemo_00.dot b/docs/source/APPNOTE_011_Design_Investigation/memdemo_00.dot
new file mode 100644
index 000000000..0336a9aac
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/memdemo_00.dot
@@ -0,0 +1,138 @@
+digraph "memdemo" {
+rankdir="LR";
+remincross=true;
+n24 [ shape=octagon, label="clk", color="black", fontcolor="black" ];
+n25 [ shape=octagon, label="d", color="black", fontcolor="black" ];
+n26 [ shape=diamond, label="mem[0]", color="black", fontcolor="black" ];
+n27 [ shape=diamond, label="mem[1]", color="black", fontcolor="black" ];
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+x0 [ shape=record, style=rounded, label="<s0> 1:1 - 0:0 " ];
+x0:e -> c41:p40:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, color="black", label=""];
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diff --git a/docs/source/APPNOTE_011_Design_Investigation/memdemo_01.dot b/docs/source/APPNOTE_011_Design_Investigation/memdemo_01.dot
new file mode 100644
index 000000000..2ad92c78b
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/memdemo_01.dot
@@ -0,0 +1,29 @@
+digraph "memdemo" {
+rankdir="LR";
+remincross=true;
+n4 [ shape=diamond, label="mem[0]", color="black", fontcolor="black" ];
+n5 [ shape=diamond, label="mem[1]", color="black", fontcolor="black" ];
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+}
diff --git a/docs/source/APPNOTE_011_Design_Investigation/primetest.v b/docs/source/APPNOTE_011_Design_Investigation/primetest.v
new file mode 100644
index 000000000..6cb766b73
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/primetest.v
@@ -0,0 +1,4 @@
+module primetest(p, a, b, ok);
+input [15:0] p, a, b;
+output ok = p != a*b || a == 1 || b == 1;
+endmodule
diff --git a/docs/source/APPNOTE_011_Design_Investigation/splice.dot b/docs/source/APPNOTE_011_Design_Investigation/splice.dot
new file mode 100644
index 000000000..4657feed1
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/splice.dot
@@ -0,0 +1,39 @@
+digraph "splice_demo" {
+rankdir="LR";
+remincross=true;
+n1 [ shape=octagon, label="a", color="black", fontcolor="black" ];
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diff --git a/docs/source/APPNOTE_011_Design_Investigation/splice.v b/docs/source/APPNOTE_011_Design_Investigation/splice.v
new file mode 100644
index 000000000..1cf7274c0
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/splice.v
@@ -0,0 +1,10 @@
+module splice_demo(a, b, c, d, e, f, x, y);
+
+input [1:0] a, b, c, d, e, f;
+output [1:0] x = {a[0], a[1]};
+
+output [11:0] y;
+assign {y[11:4], y[1:0], y[3:2]} =
+                {a, b, -{c, d}, ~{e, f}};
+
+endmodule
diff --git a/docs/source/APPNOTE_011_Design_Investigation/submod.ys b/docs/source/APPNOTE_011_Design_Investigation/submod.ys
new file mode 100644
index 000000000..29ad61076
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/submod.ys
@@ -0,0 +1,16 @@
+read_verilog memdemo.v
+proc; opt; memory; opt
+
+cd memdemo
+select -set outstage y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff
+select -set selstage y %ci2:+$dff[Q,D] %ci*:-$dff @outstage %d
+select -set scramble mem* %ci2 %ci*:-$dff mem* %d @selstage %d
+submod -name scramble @scramble
+submod -name outstage @outstage
+submod -name selstage @selstage
+
+cd ..
+show -format dot -prefix submod_00 memdemo
+show -format dot -prefix submod_01 scramble
+show -format dot -prefix submod_02 outstage
+show -format dot -prefix submod_03 selstage
diff --git a/docs/source/APPNOTE_011_Design_Investigation/submod_00.dot b/docs/source/APPNOTE_011_Design_Investigation/submod_00.dot
new file mode 100644
index 000000000..2e55268ee
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/submod_00.dot
@@ -0,0 +1,45 @@
+digraph "memdemo" {
+rankdir="LR";
+remincross=true;
+n5 [ shape=octagon, label="clk", color="black", fontcolor="black" ];
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diff --git a/docs/source/APPNOTE_011_Design_Investigation/submod_01.dot b/docs/source/APPNOTE_011_Design_Investigation/submod_01.dot
new file mode 100644
index 000000000..f8f8c008a
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/submod_01.dot
@@ -0,0 +1,87 @@
+digraph "scramble" {
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+}
diff --git a/docs/source/APPNOTE_011_Design_Investigation/submod_02.dot b/docs/source/APPNOTE_011_Design_Investigation/submod_02.dot
new file mode 100644
index 000000000..1a672c484
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/submod_02.dot
@@ -0,0 +1,33 @@
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diff --git a/docs/source/APPNOTE_011_Design_Investigation/submod_03.dot b/docs/source/APPNOTE_011_Design_Investigation/submod_03.dot
new file mode 100644
index 000000000..0dbbe3baa
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/submod_03.dot
@@ -0,0 +1,26 @@
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diff --git a/docs/source/APPNOTE_011_Design_Investigation/sumprod.v b/docs/source/APPNOTE_011_Design_Investigation/sumprod.v
new file mode 100644
index 000000000..4091bf0a1
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/sumprod.v
@@ -0,0 +1,12 @@
+module sumprod(a, b, c, sum, prod);
+
+  input [7:0] a, b, c;
+  output [7:0] sum, prod;
+
+  {* sumstuff *}
+  assign sum = a + b + c;
+  {* *}
+
+  assign prod = a * b * c;
+
+endmodule
diff --git a/docs/source/APPNOTE_011_Design_Investigation/sumprod_00.dot b/docs/source/APPNOTE_011_Design_Investigation/sumprod_00.dot
new file mode 100644
index 000000000..06522dcc9
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/sumprod_00.dot
@@ -0,0 +1,18 @@
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diff --git a/docs/source/APPNOTE_011_Design_Investigation/sumprod_01.dot b/docs/source/APPNOTE_011_Design_Investigation/sumprod_01.dot
new file mode 100644
index 000000000..aefe7a6da
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/sumprod_01.dot
@@ -0,0 +1,15 @@
+digraph "sumprod" {
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diff --git a/docs/source/APPNOTE_011_Design_Investigation/sumprod_02.dot b/docs/source/APPNOTE_011_Design_Investigation/sumprod_02.dot
new file mode 100644
index 000000000..4646c9947
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/sumprod_02.dot
@@ -0,0 +1,5 @@
+digraph "sumprod" {
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+n1 [ shape=octagon, label="prod", color="black", fontcolor="black" ];
+}
diff --git a/docs/source/APPNOTE_011_Design_Investigation/sumprod_03.dot b/docs/source/APPNOTE_011_Design_Investigation/sumprod_03.dot
new file mode 100644
index 000000000..dcfea2b56
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/sumprod_03.dot
@@ -0,0 +1,11 @@
+digraph "sumprod" {
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+v0 [ label="$3_Y" ];
+v1 [ label="c" ];
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diff --git a/docs/source/APPNOTE_011_Design_Investigation/sumprod_04.dot b/docs/source/APPNOTE_011_Design_Investigation/sumprod_04.dot
new file mode 100644
index 000000000..e77c41aa2
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/sumprod_04.dot
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new file mode 100644
index 000000000..b54441290
--- /dev/null
+++ b/docs/source/APPNOTE_011_Design_Investigation/sumprod_05.dot
@@ -0,0 +1,15 @@
+digraph "sumprod" {
+rankdir="LR";
+remincross=true;
+n2 [ shape=octagon, label="c", color="black", fontcolor="black" ];
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diff --git a/docs/source/CHAPTER_Prog.rst b/docs/source/CHAPTER_Prog.rst
index f706123aa..23aeed5a5 100644
--- a/docs/source/CHAPTER_Prog.rst
+++ b/docs/source/CHAPTER_Prog.rst
@@ -15,11 +15,11 @@ The guidelines directory contains notes on various aspects of Yosys
 development. The files GettingStarted and CodingStyle may be of
 particular interest, and are reproduced here.
 
-.. literalinclude:: ../../guidelines/GettingStarted
+.. literalinclude:: temp/GettingStarted
 	:language: none
 	:caption: guidelines/GettingStarted
 
-.. literalinclude:: ../../guidelines/CodingStyle
+.. literalinclude:: temp/CodingStyle
 	:language: none
 	:caption: guidelines/CodingStyle
 
@@ -28,19 +28,19 @@ The "stubsnets" example module
 
 The following is the complete code of the "stubsnets" example module. It
 is included in the Yosys source distribution as
-manual/CHAPTER_Prog/stubnets.cc.
+docs/source/CHAPTER_Prog/stubnets.cc.
 
-.. literalinclude:: ../../manual/CHAPTER_Prog/stubnets.cc
+.. literalinclude:: CHAPTER_Prog/stubnets.cc
 	:language: c++
 	:linenos:
-	:caption: manual/CHAPTER_Prog/stubnets.cc
+	:caption: docs/source/CHAPTER_Prog/stubnets.cc
 
-.. literalinclude:: ../../manual/CHAPTER_Prog/Makefile
+.. literalinclude:: CHAPTER_Prog/Makefile
 	:language: makefile
 	:linenos:
-	:caption: manual/CHAPTER_Prog/Makefile
+	:caption: docs/source/CHAPTER_Prog/Makefile
 
-.. literalinclude:: ../../manual/CHAPTER_Prog/test.v
+.. literalinclude:: CHAPTER_Prog/test.v
 	:language: verilog
 	:linenos:
-	:caption: manual/CHAPTER_Prog/test.v
+	:caption: docs/source/CHAPTER_Prog/test.v
diff --git a/docs/source/CHAPTER_Prog/.gitignore b/docs/source/CHAPTER_Prog/.gitignore
new file mode 100644
index 000000000..fa83c3212
--- /dev/null
+++ b/docs/source/CHAPTER_Prog/.gitignore
@@ -0,0 +1,3 @@
+stubnets.so
+stubnets.d
+*.log
diff --git a/docs/source/CHAPTER_Prog/Makefile b/docs/source/CHAPTER_Prog/Makefile
new file mode 100644
index 000000000..8e326bdc2
--- /dev/null
+++ b/docs/source/CHAPTER_Prog/Makefile
@@ -0,0 +1,12 @@
+test: stubnets.so
+	yosys -ql test1.log -m ./stubnets.so test.v -p "stubnets"
+	yosys -ql test2.log -m ./stubnets.so test.v -p "opt; stubnets"
+	yosys -ql test3.log -m ./stubnets.so test.v -p "techmap; opt; stubnets -report_bits"
+	tail test1.log test2.log test3.log
+
+stubnets.so: stubnets.cc
+	yosys-config --exec --cxx --cxxflags --ldflags -o $@ -shared $^ --ldlibs
+
+clean:
+	rm -f test1.log test2.log test3.log
+	rm -f stubnets.so stubnets.d
diff --git a/docs/source/CHAPTER_Prog/stubnets.cc b/docs/source/CHAPTER_Prog/stubnets.cc
new file mode 100644
index 000000000..566d24b18
--- /dev/null
+++ b/docs/source/CHAPTER_Prog/stubnets.cc
@@ -0,0 +1,130 @@
+// This is free and unencumbered software released into the public domain.
+//
+// Anyone is free to copy, modify, publish, use, compile, sell, or
+// distribute this software, either in source code form or as a compiled
+// binary, for any purpose, commercial or non-commercial, and by any
+// means.
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+#include <string>
+#include <map>
+#include <set>
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+// this function is called for each module in the design
+static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool report_bits)
+{
+	// use a SigMap to convert nets to a unique representation
+	SigMap sigmap(module);
+
+	// count how many times a single-bit signal is used
+	std::map<RTLIL::SigBit, int> bit_usage_count;
+
+	// count output lines for this module (needed only for summary output at the end)
+	int line_count = 0;
+
+	log("Looking for stub wires in module %s:\n", RTLIL::id2cstr(module->name));
+
+	// For all ports on all cells
+	for (auto &cell_iter : module->cells_)
+	for (auto &conn : cell_iter.second->connections())
+	{
+		// Get the signals on the port
+		// (use sigmap to get a uniqe signal name)
+		RTLIL::SigSpec sig = sigmap(conn.second);
+
+		// add each bit to bit_usage_count, unless it is a constant
+		for (auto &bit : sig)
+			if (bit.wire != NULL)
+				bit_usage_count[bit]++;
+	}
+
+	// for each wire in the module
+	for (auto &wire_iter : module->wires_)
+	{
+		RTLIL::Wire *wire = wire_iter.second;
+
+		// .. but only selected wires
+		if (!design->selected(module, wire))
+			continue;
+
+		// add +1 usage if this wire actually is a port
+		int usage_offset = wire->port_id > 0 ? 1 : 0;
+
+		// we will record which bits of the (possibly multi-bit) wire are stub signals
+		std::set<int> stub_bits;
+
+		// get a signal description for this wire and split it into separate bits
+		RTLIL::SigSpec sig = sigmap(wire);
+
+		// for each bit (unless it is a constant):
+		// check if it is used at least two times and add to stub_bits otherwise
+		for (int i = 0; i < GetSize(sig); i++)
+			if (sig[i].wire != NULL && (bit_usage_count[sig[i]] + usage_offset) < 2)
+				stub_bits.insert(i);
+
+		// continue if no stub bits found
+		if (stub_bits.size() == 0)
+			continue;
+
+		// report stub bits and/or stub wires, don't report single bits
+		// if called with report_bits set to false.
+		if (GetSize(stub_bits) == GetSize(sig)) {
+			log("  found stub wire: %s\n", RTLIL::id2cstr(wire->name));
+		} else {
+			if (!report_bits)
+				continue;
+			log("  found wire with stub bits: %s [", RTLIL::id2cstr(wire->name));
+			for (int bit : stub_bits)
+				log("%s%d", bit == *stub_bits.begin() ? "" : ", ", bit);
+			log("]\n");
+		}
+
+		// we have outputted a line, increment summary counter
+		line_count++;
+	}
+
+	// report summary
+	if (report_bits)
+		log("  found %d stub wires or wires with stub bits.\n", line_count);
+	else
+		log("  found %d stub wires.\n", line_count);
+}
+
+// each pass contains a singleton object that is derived from Pass
+struct StubnetsPass : public Pass {
+	StubnetsPass() : Pass("stubnets") { }
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		// variables to mirror information from passed options
+		bool report_bits = 0;
+
+		log_header(design, "Executing STUBNETS pass (find stub nets).\n");
+
+		// parse options
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			std::string arg = args[argidx];
+			if (arg == "-report_bits") {
+				report_bits = true;
+				continue;
+			}
+			break;
+		}
+
+		// handle extra options (e.g. selection)
+		extra_args(args, argidx, design);
+
+		// call find_stub_nets() for each module that is either
+		// selected as a whole or contains selected objects.
+		for (auto &it : design->modules_)
+			if (design->selected_module(it.first))
+				find_stub_nets(design, it.second, report_bits);
+	}
+} StubnetsPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/docs/source/CHAPTER_Prog/test.v b/docs/source/CHAPTER_Prog/test.v
new file mode 100644
index 000000000..201f75006
--- /dev/null
+++ b/docs/source/CHAPTER_Prog/test.v
@@ -0,0 +1,8 @@
+module uut(in1, in2, in3, out1, out2);
+
+input [8:0] in1, in2, in3;
+output [8:0] out1, out2;
+
+assign out1 = in1 + in2 + (in3 >> 4);
+
+endmodule
diff --git a/docs/source/appendix/APPNOTE_011_Design_Investigation.rst b/docs/source/appendix/APPNOTE_011_Design_Investigation.rst
index 004d3cb66..44819e283 100644
--- a/docs/source/appendix/APPNOTE_011_Design_Investigation.rst
+++ b/docs/source/appendix/APPNOTE_011_Design_Investigation.rst
@@ -140,7 +140,7 @@ behavior of the circuit.
 
    Output of ``yosys -p 'proc; opt; show' splice.v``
 
-.. literalinclude:: ../../../manual/APPNOTE_011_Design_Investigation/splice.v
+.. literalinclude:: ../APPNOTE_011_Design_Investigation/splice.v
    :caption: ``splice.v``
    :name: splice_src
 
@@ -355,7 +355,7 @@ Objects can not only be selected by their name but also by other properties. For
 example ``select t:$add`` will select all cells of type ``$add``. In this case
 this is also yields the diagram shown in :numref:`seladd`.
 
-.. literalinclude:: ../../../manual/APPNOTE_011_Design_Investigation/foobaraddsub.v
+.. literalinclude:: ../APPNOTE_011_Design_Investigation/foobaraddsub.v
    :caption: Test module for operations on selections
    :name: foobaraddsub
    :language: verilog
@@ -380,7 +380,7 @@ which is a complete selection of everything in the current module.
 Operations on selections
 ------------------------
 
-.. literalinclude:: ../../../manual/APPNOTE_011_Design_Investigation/sumprod.v
+.. literalinclude:: ../APPNOTE_011_Design_Investigation/sumprod.v
    :caption: Another test module for operations on selections
    :name: sumprod
    :language: verilog
@@ -487,7 +487,7 @@ features. We synthesize the circuit using ``proc; opt; memory; opt`` and change
 to the ``memdemo`` module with ``cd memdemo``. If we type ``show`` now we see
 the diagram shown in :numref:`memdemo_00`.
 
-.. literalinclude:: ../../../manual/APPNOTE_011_Design_Investigation/memdemo.v
+.. literalinclude:: ../APPNOTE_011_Design_Investigation/memdemo.v
    :caption: Demo circuit for demonstrating some advanced Yosys features
    :name: memdemo_src
    :language: verilog
@@ -685,7 +685,7 @@ commands can be applied.
 Solving combinatorial SAT problems
 ----------------------------------
 
-.. literalinclude:: ../../../manual/APPNOTE_011_Design_Investigation/primetest.v
+.. literalinclude:: ../APPNOTE_011_Design_Investigation/primetest.v
    :language: verilog
    :caption: A simple miter circuit for testing if a number is prime. But it has
              a problem (see main text and :numref:`primesat`).