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| author | Jannis Harder <me@jix.one> | 2023-02-15 13:45:00 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-02-15 13:45:00 +0100 |
| commit | 1c667fab2b02d43554db13292d49863e340ff277 (patch) | |
| tree | f13c65f0fc41258fccde5e188ad66d27dbc74567 /docs | |
| parent | 1cedad7a685d08f6369a0dbbe1facb884e9cc880 (diff) | |
| parent | 1698202ccc2f62d581673fd1320c3ab137f0261a (diff) | |
| download | yosys-1c667fab2b02d43554db13292d49863e340ff277.tar.gz yosys-1c667fab2b02d43554db13292d49863e340ff277.tar.bz2 yosys-1c667fab2b02d43554db13292d49863e340ff277.zip | |
Merge pull request #3672 from jix/yw-cosim-hierarchy-fixes
sim: For yw cosim, drive parent module's signals for input ports
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