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| author | TaoBi22 <beahealy22@gmail.com> | 2022-09-28 12:42:27 +0100 |
|---|---|---|
| committer | myrtle <gatecat@ds0.me> | 2022-11-17 13:34:58 +0100 |
| commit | 2b07e01ea400e2a1964d3698b3f1509685f565a2 (patch) | |
| tree | 314165e158d937a9d69ff4dc60a0531e59557505 /docs/images/overview_rtlil.tex | |
| parent | df5617856781aca9a09a647f72817c076e5e55fe (diff) | |
| download | yosys-2b07e01ea400e2a1964d3698b3f1509685f565a2.tar.gz yosys-2b07e01ea400e2a1964d3698b3f1509685f565a2.tar.bz2 yosys-2b07e01ea400e2a1964d3698b3f1509685f565a2.zip | |
Replace synth call with components, reintroduce flags and correct vpr flag implementation
Diffstat (limited to 'docs/images/overview_rtlil.tex')
0 files changed, 0 insertions, 0 deletions