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author | Ahmed Irfan <ahmedirfan1983@gmail.com> | 2014-01-14 12:03:53 +0100 |
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committer | Ahmed Irfan <ahmedirfan1983@gmail.com> | 2014-01-14 12:03:53 +0100 |
commit | 661b5a993ebbe331c8d4085372622587e1712ab4 (patch) | |
tree | 4cb07152173ff610346e1a7675ce765c1dd2ccce /btor.ys | |
parent | 1091c24d0028850699ba209469f03b28ebc66e10 (diff) | |
download | yosys-661b5a993ebbe331c8d4085372622587e1712ab4.tar.gz yosys-661b5a993ebbe331c8d4085372622587e1712ab4.tar.bz2 yosys-661b5a993ebbe331c8d4085372622587e1712ab4.zip |
BTOR backend
Diffstat (limited to 'btor.ys')
-rw-r--r-- | btor.ys | 11 |
1 files changed, 6 insertions, 5 deletions
@@ -4,7 +4,8 @@ ################# #converting processes to cells proc; -opt; +opt; opt_const -mux_undef; opt; +rename -hide;;; #converting pmux to mux techmap -map techlibs/common/pmux2mux.v; opt; @@ -12,9 +13,9 @@ opt; memory_dff; opt; #flatten design -flatten; -opt; -#adding temporary wires for cell ports -scatter; +flatten;;; +#cell output to be a single wire +splitnets -driver; +opt;;; #writing btor write_btor design.btor; |