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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 20:15:09 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-02 12:13:25 -0700 |
commit | f76cb584940fa3217de28febdb103443b8a8cf37 (patch) | |
tree | a8d0d54a11305713556ac63e882fc02a38536cc9 /backends | |
parent | 17b77fd41197b64f79bbbb59088e9de623d84716 (diff) | |
download | yosys-f76cb584940fa3217de28febdb103443b8a8cf37.tar.gz yosys-f76cb584940fa3217de28febdb103443b8a8cf37.tar.bz2 yosys-f76cb584940fa3217de28febdb103443b8a8cf37.zip |
Recognise built-in types (e.g. $_DFF_*)
Diffstat (limited to 'backends')
-rw-r--r-- | backends/aiger/xaiger.cc | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 77d0e94c2..e1b84236d 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -261,11 +261,12 @@ struct XAigerWriter } } else { - bool cell_known = cell->known(); + bool cell_known = inst_module || cell->known(); for (const auto &c : cell->connections()) { if (c.second.is_fully_const()) continue; - auto is_input = !cell_known || cell->input(c.first); - auto is_output = !cell_known || cell->output(c.first); + auto port_wire = inst_module ? inst_module->wire(c.first) : nullptr; + auto is_input = (port_wire && port_wire->port_input) || !cell_known || cell->input(c.first); + auto is_output = (port_wire && port_wire->port_output) || !cell_known || cell->output(c.first); if (!is_input && !is_output) log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type)); |