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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 12:29:28 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 12:29:28 -0800 |
| commit | f2576c096cedf0974f237530a9d50e250bf117a3 (patch) | |
| tree | 3f5a0653615a125b0b51a2b135f5ac6d0b95794b /backends | |
| parent | b0605128b633f64b07107ba3a673f406e96d42ad (diff) | |
| parent | 9009b76a69b9e867f69295a8e555305925e83aeb (diff) | |
| download | yosys-f2576c096cedf0974f237530a9d50e250bf117a3.tar.gz yosys-f2576c096cedf0974f237530a9d50e250bf117a3.tar.bz2 yosys-f2576c096cedf0974f237530a9d50e250bf117a3.zip | |
Merge branch 'eddie/abc9_refactor' into eddie/abc9_required
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 6 | ||||
| -rw-r--r-- | backends/edif/edif.cc | 2 |
2 files changed, 5 insertions, 3 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 71b652412..76b7efbfc 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -222,6 +222,8 @@ struct XAigerWriter alias_map[Q] = D; auto r YS_ATTRIBUTE(unused) = ff_bits.insert(std::make_pair(D, cell)); log_assert(r.second); + if (input_bits.erase(Q)) + log_assert(Q.wire->attributes.count(ID::keep)); continue; } @@ -589,9 +591,6 @@ struct XAigerWriter // write_o_buffer(0); if (!box_list.empty() || !ff_bits.empty()) { - RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str())); - log_assert(holes_module); - dict<IdString, std::tuple<int,int,int>> cell_cache; int box_count = 0; @@ -678,6 +677,7 @@ struct XAigerWriter f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be)); f.write(buffer_str.data(), buffer_str.size()); + RTLIL::Module *holes_module = module->design->module(stringf("%s$holes", module->name.c_str())); if (holes_module) { std::stringstream a_buffer; XAigerWriter writer(holes_module, true /* holes_mode */); diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 6735d670f..60a098917 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -412,6 +412,8 @@ struct EdifBackend : public Backend { for (auto &ref : it.second) log_warning("Exporting x-bit on %s as zero bit.\n", ref.c_str()); sig = RTLIL::State::S0; + } else if (sig == RTLIL::State::Sz) { + continue; } else { for (auto &ref : it.second) log_error("Don't know how to handle %s on %s.\n", log_signal(sig), ref.c_str()); |