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| author | Clifford Wolf <clifford@clifford.at> | 2016-08-15 08:26:20 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-08-15 08:26:20 +0200 |
| commit | f0a8713fea9fea016e5a83fefd9e00a32f4a88d2 (patch) | |
| tree | ea36bef66648cf394954fcaf36ca69473e724bc9 /backends | |
| parent | 1058660ac882d97bd41737627c6246948edcab90 (diff) | |
| download | yosys-f0a8713fea9fea016e5a83fefd9e00a32f4a88d2.tar.gz yosys-f0a8713fea9fea016e5a83fefd9e00a32f4a88d2.tar.bz2 yosys-f0a8713fea9fea016e5a83fefd9e00a32f4a88d2.zip | |
Fixed upto handling in verilog back-end
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index caa668c33..705d74aa1 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -141,6 +141,9 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string ®_name) if (sig.size() != chunk.wire->width) { if (sig.size() == 1) reg_name += stringf("[%d]", chunk.wire->start_offset + chunk.offset); + else if (chunk.wire->upto) + reg_name += stringf("[%d:%d]", (chunk.wire->width - (chunk.offset + chunk.width - 1) - 1) + chunk.wire->start_offset, + (chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset); else reg_name += stringf("[%d:%d]", chunk.wire->start_offset + chunk.offset + chunk.width - 1, chunk.wire->start_offset + chunk.offset); |