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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 12:46:55 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-21 12:46:55 -0700 |
| commit | ea154d5ff472e4e18abc7c6328fb8072b84f6582 (patch) | |
| tree | 48e5f36349f6b80247bf297a684ee696c120ed59 /backends | |
| parent | 950bb4c2428aa546ee6abc861e7e87fea31a4b20 (diff) | |
| download | yosys-ea154d5ff472e4e18abc7c6328fb8072b84f6582.tar.gz yosys-ea154d5ff472e4e18abc7c6328fb8072b84f6582.tar.bz2 yosys-ea154d5ff472e4e18abc7c6328fb8072b84f6582.zip | |
No point logging constant bit
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 0e8ea65bf..b7a5d5761 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -110,7 +110,7 @@ struct XAigerWriter } if (bit == State::Sx || bit == State::Sz) { - log_debug("Bit '%s' contains 'x' or 'z' bits. Treating as 1'b0.\n", log_signal(bit)); + log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n"); a = aig_map.at(State::S0); } |