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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-15 22:25:37 -0700 | 
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-15 22:25:37 -0700 | 
| commit | e084240a813b618cea6b5a80d41e2d4516388e44 (patch) | |
| tree | 9d23e1b3fd6e3fac8e8fee1115929494f0b4ef01 /backends | |
| parent | 8fbbd9b129697152c93c35831c1d50982702a3ec (diff) | |
| download | yosys-e084240a813b618cea6b5a80d41e2d4516388e44.tar.gz yosys-e084240a813b618cea6b5a80d41e2d4516388e44.tar.bz2 yosys-e084240a813b618cea6b5a80d41e2d4516388e44.zip  | |
Check abc_box_id attr
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 17 | 
1 files changed, 16 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index d3384e136..eb31bfcef 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -212,6 +212,8 @@ struct XAigerWriter  				continue;  			} +			bool abc_box = module->design->module(cell->type)->attributes.count("\\abc_box_id"); +  			for (const auto &c : cell->connections()) {  				/*if (c.second.is_fully_const()) continue;*/  				for (auto b : c.second.bits()) { @@ -224,20 +226,33 @@ struct XAigerWriter  							if (I != b)  								alias_map[b] = I;  							/*if (!output_bits.count(b))*/ +							if (abc_box)  								co_bits.emplace_back(b, 0); +							else { +								output_bits.insert(b); +								if (!b.wire->port_input) +									unused_bits.erase(b); +							}  						}  					}  					if (is_output) {  						SigBit O = sigmap(b);  						/*if (!input_bits.count(O))*/ +						if (abc_box)  							ci_bits.emplace_back(O, 0); +						else { +							input_bits.insert(O); +							if (!O.wire->port_output) +								undriven_bits.erase(O); +						}  					}  				}  				if (!type_map.count(cell->type))  					type_map[cell->type] = type_map.size()+1;  			} -			box_list.emplace_back(cell); +			if (abc_box) +				box_list.emplace_back(cell);  			//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));  		}  | 
