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| author | whitequark <whitequark@whitequark.org> | 2020-06-12 00:35:18 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-06-12 00:35:18 +0000 |
| commit | d5ecd4a570a34f5315824a5bfbd740f7fb1866fa (patch) | |
| tree | 4bbaa1a43199a298fc1039b875ae412ce96ce341 /backends | |
| parent | 29bd81d66239b22ffdbe1f72416624823d712d34 (diff) | |
| download | yosys-d5ecd4a570a34f5315824a5bfbd740f7fb1866fa.tar.gz yosys-d5ecd4a570a34f5315824a5bfbd740f7fb1866fa.tar.bz2 yosys-d5ecd4a570a34f5315824a5bfbd740f7fb1866fa.zip | |
cxxrtl: annotate port direction as comments.
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/cxxrtl/cxxrtl_backend.cc | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index c6b8bbc47..a4ef38128 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -1448,7 +1448,14 @@ struct CxxrtlWorker { } dump_attrs(wire); - f << indent << (unbuffered_wires[wire] ? "value" : "wire") << "<" << width << "> " << mangle(wire); + f << indent; + if (wire->port_input && wire->port_output) + f << "/*inout*/ "; + else if (wire->port_input) + f << "/*input*/ "; + else if (wire->port_output) + f << "/*output*/ "; + f << (unbuffered_wires[wire] ? "value" : "wire") << "<" << width << "> " << mangle(wire); if (wire->has_attribute(ID::init)) { f << " "; dump_const_init(wire->attributes.at(ID::init)); |