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authorEddie Hung <eddie@fpgeh.com>2020-01-03 14:59:55 -0800
committerEddie Hung <eddie@fpgeh.com>2020-01-03 14:59:55 -0800
commita819656972dd44c479422fa688874926d6239a95 (patch)
treed921a90e8175571e3f5da4f25791bd1ede3007f0 /backends
parent559f3379e852f304a0255afcc37714b9d0da59d9 (diff)
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WIP
Diffstat (limited to 'backends')
-rw-r--r--backends/aiger/xaiger.cc56
1 files changed, 0 insertions, 56 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index ff3de65cc..e9b4f07bf 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -336,8 +336,6 @@ struct XAigerWriter
}
}
- bool blackbox = box_module->get_blackbox_attribute(true /* ignore_wb */);
-
// Fully pad all unused input connections of this box cell with S0
// Fully pad all undriven output connections of this box cell with anonymous wires
for (auto port_name : r.first->second) {
@@ -615,65 +613,11 @@ struct XAigerWriter
if (holes_module) {
log_push();
- // NB: fixup_ports() will sort ports by name
- //holes_module->fixup_ports();
- holes_module->check();
-
- // Cannot techmap/aigmap/check all lib_whitebox-es outside of write_xaiger
- // since boxes may contain parameters in which case `flatten` would have
- // created a new $paramod ...
- Pass::call_on_module(holes_module->design, holes_module, "wbflip");
- Pass::call_on_module(holes_module->design, holes_module, "flatten -wb; techmap; aigmap");
-
- dict<SigSig, SigSig> replace;
- for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
- auto cell = it->second;
- if (cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
- "$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_")) {
- SigBit D = cell->getPort("\\D");
- SigBit Q = cell->getPort("\\Q");
- // Remove the DFF cell from what needs to be a combinatorial box
- it = holes_module->cells_.erase(it);
- Wire *port;
- if (GetSize(Q.wire) == 1)
- port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
- else
- port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
- log_assert(port);
- // Prepare to replace "assign <port> = DFF.Q;" with "assign <port> = DFF.D;"
- // in order to extract the combinatorial control logic that feeds the box
- // (i.e. clock enable, synchronous reset, etc.)
- replace.insert(std::make_pair(SigSig(port,Q), SigSig(port,D)));
- // Since `flatten` above would have created wires named "<cell>.Q",
- // extract the pre-techmap cell name
- auto pos = Q.wire->name.str().rfind(".");
- log_assert(pos != std::string::npos);
- IdString driver = Q.wire->name.substr(0, pos);
- // And drive the signal that was previously driven by "DFF.Q" (typically
- // used to implement clock-enable functionality) with the "<cell>.abc9_ff.Q"
- // wire (which itself is driven an input port) we inserted above
- Wire *currQ = holes_module->wire(stringf("%s.abc9_ff.Q", driver.c_str()));
- log_assert(currQ);
- holes_module->connect(Q, currQ);
- continue;
- }
- else if (!cell->type.in("$_NOT_", "$_AND_"))
- log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
- ++it;
- }
-
- for (auto &conn : holes_module->connections_) {
- auto it = replace.find(conn);
- if (it != replace.end())
- conn = it->second;
- }
-
// Move into a new (temporary) design so that "clean" will only
// operate (and run checks on) this one module
RTLIL::Design *holes_design = new RTLIL::Design;
module->design->modules_.erase(holes_module->name);
holes_design->add(holes_module);
- Pass::call(holes_design, "opt -purge");
std::stringstream a_buffer;
XAigerWriter writer(holes_module);