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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 15:55:02 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 15:55:02 -0700 |
| commit | 8374eb1cb4dcb99b2125543a3d5f9f6adbdd6b7d (patch) | |
| tree | c714c96b4c9e3fd2e9311cb0101a0bfc130b06a3 /backends | |
| parent | 2e7e73f483e32fec62bc14fc12b10dafb17082f5 (diff) | |
| download | yosys-8374eb1cb4dcb99b2125543a3d5f9f6adbdd6b7d.tar.gz yosys-8374eb1cb4dcb99b2125543a3d5f9f6adbdd6b7d.tar.bz2 yosys-8374eb1cb4dcb99b2125543a3d5f9f6adbdd6b7d.zip | |
Remove unnecessary undriven_bits.insert
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 3a4b353e2..fcf9a7bf1 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -154,11 +154,8 @@ struct XAigerWriter } if (wire->port_output || keep) { - if (bit != wirebit) { + if (bit != wirebit) alias_map[wirebit] = bit; - if (!bit.wire) - undriven_bits.insert(wirebit); - } output_bits.insert(wirebit); } } |