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| author | Jannis Harder <me@jix.one> | 2022-08-02 15:55:54 +0200 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2022-08-16 13:37:30 +0200 |
| commit | 5893cae6472727a71573cb0826158125a6aa04af (patch) | |
| tree | 3bf668f4a8b2898b950dc1597be3c6b7b730455b /backends | |
| parent | 021c3c8da52ebaf6088ea740fdc12b496bfc338a (diff) | |
| download | yosys-5893cae6472727a71573cb0826158125a6aa04af.tar.gz yosys-5893cae6472727a71573cb0826158125a6aa04af.tar.bz2 yosys-5893cae6472727a71573cb0826158125a6aa04af.zip | |
aiger: Support $anyinit cells
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/aiger.cc | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index 547d131ee..800743b22 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -189,6 +189,17 @@ struct AigerWriter continue; } + if (cell->type == ID($anyinit)) + { + auto sig_d = sigmap(cell->getPort(ID::D)); + auto sig_q = sigmap(cell->getPort(ID::Q)); + for (int i = 0; i < sig_d.size(); i++) { + undriven_bits.erase(sig_q[i]); + ff_map[sig_q[i]] = sig_d[i]; + } + continue; + } + if (cell->type == ID($_AND_)) { SigBit A = sigmap(cell->getPort(ID::A).as_bit()); |