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author | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 14:27:29 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-14 14:27:29 -0800 |
commit | 4656f202c6f05d126c1acc79fca675e467c80840 (patch) | |
tree | b6c3fbb378cfb0191492260220289e7a3ae2502e /backends | |
parent | 654247abe9078566f93960a135ce08b0cfc96442 (diff) | |
download | yosys-4656f202c6f05d126c1acc79fca675e467c80840.tar.gz yosys-4656f202c6f05d126c1acc79fca675e467c80840.tar.bz2 yosys-4656f202c6f05d126c1acc79fca675e467c80840.zip |
abc9_ops: -reintegrate to not trim box padding anymore
Diffstat (limited to 'backends')
-rw-r--r-- | backends/aiger/xaiger.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index f9890a592..4f466d568 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -349,7 +349,7 @@ struct XAigerWriter unused_bits.erase(I); } if (w->port_output) - for (const auto &b : rhs.bits()) { + for (const auto &b : rhs) { SigBit O = sigmap(b); if (O != b) alias_map[O] = b; |