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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 12:25:26 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-07 12:25:26 -0700 |
| commit | 3414ee1e3fe37d4bf383621542828d4fc8fc987f (patch) | |
| tree | 470091b56756df8073dadba84344aab0213de53c /backends | |
| parent | 5545cd3c108ef240ccf6278b2734412acf81cd2a (diff) | |
| parent | 58e512ab7082ad5b4884dc0edc197b56c642bc94 (diff) | |
| download | yosys-3414ee1e3fe37d4bf383621542828d4fc8fc987f.tar.gz yosys-3414ee1e3fe37d4bf383621542828d4fc8fc987f.tar.bz2 yosys-3414ee1e3fe37d4bf383621542828d4fc8fc987f.zip | |
Merge pull request #1248 from YosysHQ/eddie/abc9_speedup
abc9: speedup by using using "clean" more efficiently
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/aiger/xaiger.cc | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index a3a753912..36a379e34 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -621,8 +621,7 @@ struct XAigerWriter log_debug("boxNum = %d\n", GetSize(box_list)); write_h_buffer(box_list.size()); - RTLIL::Module *holes_module = nullptr; - holes_module = module->design->addModule("$__holes__"); + RTLIL::Module *holes_module = module->design->addModule("$__holes__"); log_assert(holes_module); int port_id = 1; @@ -719,27 +718,33 @@ struct XAigerWriter Pass::call(holes_module->design, "flatten -wb"); // TODO: Should techmap/aigmap/check all lib_whitebox-es just once, - // instead of per write_xaiger call + // instead of per write_xaiger call Pass::call(holes_module->design, "techmap"); Pass::call(holes_module->design, "aigmap"); for (auto cell : holes_module->cells()) if (!cell->type.in("$_NOT_", "$_AND_")) log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n"); - Pass::call(holes_module->design, "clean -purge"); + holes_module->design->selection_stack.pop_back(); + + // Move into a new (temporary) design so that "clean" will only + // operate (and run checks on) this one module + RTLIL::Design *holes_design = new RTLIL::Design; + holes_module->design->modules_.erase(holes_module->name); + holes_design->add(holes_module); + Pass::call(holes_design, "clean -purge"); std::stringstream a_buffer; XAigerWriter writer(holes_module, true /* holes_mode */); writer.write_aiger(a_buffer, false /*ascii_mode*/); - holes_module->design->selection_stack.pop_back(); + delete holes_design; f << "a"; std::string buffer_str = a_buffer.str(); int32_t buffer_size_be = to_big_endian(buffer_str.size()); f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be)); f.write(buffer_str.data(), buffer_str.size()); - holes_module->design->remove(holes_module); log_pop(); } |